公开(公告)号：US20210304944A1

公开(公告)日：2021-09-30

申请号：US16835227

申请日：2020-03-30

Applicant: QUALCOMM Incorporated

Inventor： Kai LIU ,  Xiaoju YU ,  Xia LI ,  Bin YANG

IPC: H01F27/22 ,  H01G4/33 ,  H01G4/252 ,  H01F27/29

Abstract: Examples herein include thermally conductive pathways for glass substrates such as used by passive on glass devices that may be used to enhance the thermal conductivity of an integrated POG device. By using a thermally conductive material for passivation of the device pathways during manufacturing, the device pathways may be able to conduct heat away from the device. For example, by using a selected poly (p-phenylene benzobisoxazole) (PBO) based material (e.g., poly-p-phenylene-2, 6-benzobisoxazole) instead of conventional polyimide (PI) materials during a Cu pattern passivation process, the overall thermal performance of the device, may be enhanced.

公开(公告)号：US20190356294A1

公开(公告)日：2019-11-21

申请号：US15982655

申请日：2018-05-17

Applicant: QUALCOMM Incorporated

Inventor： Nosun PARK ,  Changhan Hobie YUN ,  Jonghae KIM ,  Niranjan Sunil MUDAKATTE ,  Xiaoju YU ,  Wei-Chuan CHEN

IPC: H03H7/01 ,  H03H1/00 ,  H03H3/00 ,  H01F27/40 ,  H01L49/02 ,  H01L27/01 ,  H01L23/29 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L21/683 ,  H01L25/16

Abstract: A three-dimensional (3D) solenoid structure includes a first inductor portion having a first surface and a second surface opposite the first surface. The 3D solenoid structure further includes a first capacitor portion, a first inductor pillar, at least one capacitor pillar, a second inductor portion, a second inductor pillar and a first inductor bonding interface. The first inductor pillar is coupled to the first surface of the first inductor portion. The capacitor pillar(s) is coupled to the first capacitor portion. The second inductor portion includes a first surface and a second surface opposite the first surface. The second inductor pillar is coupled to the first surface of the second inductor portion. The first inductor bonding interface, between the first inductor pillar and the second inductor pillar, couples together the first inductor portion and the second inductor portion.

公开(公告)号：US20210098320A1

公开(公告)日：2021-04-01

申请号：US16590299

申请日：2019-10-01

Applicant: QUALCOMM Incorporated

Inventor： Daniel GARCIA ,  Kinfegebriel Amera MENGISTIE ,  Francesco CARRARA ,  Chang-Ho LEE ,  Ashish ALAWANI ,  Mark KUHLMAN ,  John Jong-Hoon LEE ,  Jeongkeun KIM ,  Xiaoju YU ,  Supatta NIRAMARNKARN

IPC: H01L23/16 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: A package that includes a substrate having a first surface; a solder resist layer coupled to the first surface of the substrate; a device located over the solder resist layer such that a portion of the device touches the solder resist layer; and an encapsulation layer located over the solder resist layer such that the encapsulation layer encapsulates the device. The solder resist layer is configured as a seating plane for the device. The device is located over the solder resist layer such that a surface of the device facing the substrate is approximately parallel to the first surface of the substrate. The solder resist layer includes at least one notch. The device is located over the solder resist layer such that at least one corner of the device touches the at least one notch.

公开(公告)号：US20200020473A1

公开(公告)日：2020-01-16

申请号：US16035378

申请日：2018-07-13

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie YUN ,  Mario Francisco VELEZ ,  Nosun PARK ,  Wei-Chuan CHEN ,  Niranjan Sunil MUDAKATTE ,  Xiaoju YU ,  Paragkumar Ajaybhai THADESAR ,  Jonghae KIM

IPC: H01F17/00 ,  H01L49/02 ,  H01L23/522 ,  H01L27/02

Abstract: Aspects of the present disclosure provide three-dimensional (3D) through-glass-via (TGV) inductors for use in electronic devices. In some embodiments, a first portion of a 3D TGV inductor may be formed in a first wafer and a second portion of a 3D TGV may be formed in a second wafer. The first portion and second portion may be bonded together in a bonded wafer device thereby forming a larger inductor occupying relatively little wafer space on the first and the second wafers.

公开(公告)号：US20210057404A1

公开(公告)日：2021-02-25

申请号：US16990418

申请日：2020-08-11

Applicant: QUALCOMM Incorporated

Inventor： Kai LIU ,  Xiaoju YU ,  Ye LU

IPC: H01L27/01 ,  H01L27/02 ,  H01L23/60

Abstract: Disclosed are devices and methods for on-die electrostatic discharge (ESD) protection in an electronic device. Aspects disclosed include an electronic device including a protected circuit disposed within a die having a first port and a second port. A first inductor is also disposed within the die and is electrically coupled to the first port. A second inductor is also disposed within the die and electrically coupled to the second port. The first inductor and the second inductor are routed in close proximity and are configured so the first inductor is out of phase with the second inductor.

公开(公告)号：US20190035621A1

公开(公告)日：2019-01-31

申请号：US15659591

申请日：2017-07-25

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie YUN ,  Mario Francisco VELEZ ,  David Francis BERDY ,  Chengjie ZUO ,  Jonghae KIM ,  Niranjan Sunil MUDAKATTE ,  Xiaoju YU

IPC: H01L21/02 ,  H01L21/67 ,  H01L23/15 ,  H01L21/20

Abstract: To overcome the deficiencies of conventional rectangular circuit wafers, a glass substrate circuit wafer with an obtuse angle on the perimeter may be used. In one example, a glass substrate wafer may include a first circuit on a first portion of a glass substrate and a second circuit on a second portion of the glass substrate where the first portion has a first obtuse angle and the second portion has a second obtuse angle that is complementary to the first obtuse angle on the perimeter of the first portion to mate together to form an outer perimeter that comprises right angles.

公开(公告)号：US20200091094A1

公开(公告)日：2020-03-19

申请号：US16132323

申请日：2018-09-14

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie YUN ,  Mario Francisco VELEZ ,  Nosun PARK ,  Niranjan Sunil MUDAKATTE ,  Wei-Chuan CHEN ,  Paragkumar Ajaybhai THADESAR ,  Christopher POLLOCK ,  Xiaoju YU ,  Rongguo ZHOU ,  Kai LIU ,  Jonghae KIM

IPC: H01L23/64 ,  H01L23/31 ,  H01L23/15 ,  H03H9/54 ,  H03H9/64 ,  H03H7/01 ,  H03H3/02 ,  H03H3/08

Abstract: A filter including an insulating die having a plurality of MIM (Metal Insulator Metal) capacitors disposed within the die is disclosed. A 2.5D (2.5 Dimensional) inductor disposed within a redistribution layer (RDL) is electrically coupled to at least one of the plurality of MIM capacitors in the die. A 3D (3 Dimensional) inductor is disposed around the die and is electrically coupled to at least one of the plurality of MIM capacitors.

公开(公告)号：US20190132942A1

公开(公告)日：2019-05-02

申请号：US15798071

申请日：2017-10-30

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie YUN ,  Jonghae KIM ,  Xiaoju YU ,  Mario Francisco VELEZ ,  Wei-Chuan CHEN ,  Niranjan Sunil MUDAKATTE ,  Matthew Michael NOWAK ,  Christian HOFFMANN ,  Rodrigo PACHER FERNANDES ,  Manuel HOFER ,  Peter BAINSCHAB ,  Edgar SCHMIDHAMMER ,  Stefan Leopold HATZL

IPC: H05K1/02 ,  H03H9/02 ,  H05K3/32

CPC classification number: H05K1/0233 ,  H03H3/02 ,  H03H3/08 ,  H03H9/02086 ,  H03H9/0547 ,  H03H9/1014 ,  H03H9/1071 ,  H05K3/32

Abstract: A passive on glass (POG) on filter capping apparatus may include an acoustic filter die. The apparatus may further include a capping die electrically coupled to the acoustic filter die. The capping die may include a 3D inductor.