公开(公告)号：US20160005749A1

公开(公告)日：2016-01-07

申请号：US14321593

申请日：2014-07-01

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Bin YANG ,  Daniel Wayne PERRY

IPC: H01L27/115 ,  H01L49/02 ,  H01L21/28

CPC classification number: H01L27/11521 ,  G11C11/223 ,  G11C16/0433 ,  H01L27/11507 ,  H01L27/1159 ,  H01L28/56 ,  H01L29/40114 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7881

Abstract: Implementations of the technology described herein provide a Multiple Time Programmable (MTP) device, such as a Flash memory device, that implements a coupling gate in series with a floating gate. The coupling gate includes a ferroelectric capacitor and a conventional capacitor. The ferroelectric capacitor in combination with the coupling gate provides a negative capacitance such that the total capacitance of the combination of the floating gate and the coupling gate is larger than it would be if the coupling gate included only a conventional capacitor. One advantage of this device is that the effective coupling ratio between the coupling gate and the floating gate is increased. Another advantage is that the floating gate drops more voltage than conventional Multiple Time Programmable (MTP) devices.

Abstract translation: 本文描述的技术的实现提供了实现与浮动栅极串联的耦合门的多时间可编程（MTP）设备，诸如闪存设备。 耦合栅极包括铁电电容器和常规电容器。 铁电电容器与耦合栅极组合提供负电容，使得浮栅和耦合栅的组合的总电容大于如果耦合栅仅包括常规电容器的总电容。 该器件的一个优点是耦合栅极和浮置栅极之间的有效耦合比增加。 另一个优点是浮动栅极比传统的多时间可编程（MTP）器件降低了更多的电压。

公开(公告)号：US20150333072A1

公开(公告)日：2015-11-19

申请号：US14280213

申请日：2014-05-16

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Zhongze WANG ,  Daniel Wayne PERRY

IPC: H01L27/112 ,  G11C7/00 ,  G11C11/40

CPC classification number: H01L27/112 ,  G11C7/00 ,  G11C11/40 ,  G11C16/0475 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/66833 ,  H01L29/7923

Abstract: An advanced metal-nitride-oxide-silicon (MNOS) multiple time programmable (MTP) memory is provided. In an example, an apparatus includes a two field effect transistor (2T field FET) metal-nitride-oxide-silicon (MNOS) MTP memory. The 2T field FET MNOS MTP memory can include an interlayer dielectric (ILD) oxide region that is formed on a well and separates respective gates of first and second transistors from the well. A control gate is located between the respective gates of the first and second transistors, and a silicon-nitride-oxide (SiN) region is located between a metal portion of the control gate and a portion of the ILD oxide region.

Abstract translation: 提供先进的金属氮化物 - 氧化物 - 硅（MNOS）多时间可编程（MTP）存储器。 在一个示例中，装置包括两个场效应晶体管（2T场FET）金属氮化物 - 氧化物 - 硅（MNOS）MTP存储器。 2T场FET MNOS MTP存储器可以包括形成在阱上的层间电介质（ILD）氧化物区域，并将第一和第二晶体管的相应栅极与阱分离。 控制栅极位于第一和第二晶体管的各个栅极之间，并且氮化硅 - 氧化物（SiN）区域位于控制栅极的金属部分和ILD氧化物区域的一部分之间。