公开(公告)号：US10340370B2

公开(公告)日：2019-07-02

申请号：US15371512

申请日：2016-12-07

Applicant: QUALCOMM Incorporated

Inventor： Hao Wang ,  Haining Yang ,  Xiaonan Chen

IPC: H01L29/739 ,  H01L27/02 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49

Abstract: Asymmetric gated fin field effect transistor (FET) (finFET) diodes are disclosed. In one aspect, an asymmetric gated finFET diode employs a substrate that includes a well region of a first-type and a fin disposed in a direction. A first source/drain region is employed that includes a first-type doped material disposed in the fin having a first length in the direction. A second source/drain region having a second length in the direction larger than the first length is employed that includes a second-type doped material disposed in the fin. A gate region is disposed between the first source/drain region and the second source/drain region and has a third length in the direction that is larger than the first length and larger than the second length. The wider gate region increases a length of a depletion region of the asymmetric gated finFET diode, which reduces current leakage while avoiding increase in area.

公开(公告)号：US09508439B2

公开(公告)日：2016-11-29

申请号：US14602090

申请日：2015-01-21

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Jeffrey Junhao Xu ,  Xiao Lu ,  Matthew Michael Nowak ,  Seung Hyuk Kang ,  Xiaonan Chen ,  Zhongze Wang ,  Yu Lu

IPC: G11C16/10 ,  H01L29/423 ,  H01L29/792 ,  H01L29/51 ,  G11C16/26 ,  H01L27/112

CPC classification number: G11C16/10 ,  G11C11/223 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C16/26 ,  H01L27/11246 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7836 ,  H01L29/792

Abstract: An apparatus includes a multiple time programmable (MTP) memory device. The MTP memory device includes a metal gate, a substrate material, and an oxide structure between the metal gate and the substrate material. The oxide structure includes a hafnium oxide layer and a silicon dioxide layer. The hafnium oxide layer is in contact with the metal gate and in contact with the silicon dioxide layer. The silicon dioxide layer is in contact with the substrate material. The MTP device includes a transistor, and a non-volatile state of the MTP memory device is based on a threshold voltage of the transistor.

Abstract translation: 一种装置包括多时间可编程（MTP）存储器件。 MTP存储器件包括金属栅极，衬底材料和金属栅极和衬底材料之间的氧化物结构。 氧化物结构包括氧化铪层和二氧化硅层。 氧化铪层与金属栅极接触并与二氧化硅层接触。 二氧化硅层与衬底材料接触。 MTP器件包括晶体管，并且MTP存储器件的非易失性状态基于晶体管的阈值电压。

公开(公告)号：US20160012896A1

公开(公告)日：2016-01-14

申请号：US14602090

申请日：2015-01-21

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Jeffrey Junhao Xu ,  Xiao Lu ,  Matthew Michael Nowak ,  Seung Hyuk Kang ,  Xiaonan Chen ,  Zhongze Wang ,  Yu Lu

IPC: G11C16/10 ,  H01L29/423 ,  H01L29/792 ,  G11C16/26 ,  H01L29/51

CPC classification number: G11C16/10 ,  G11C11/223 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C16/26 ,  H01L27/11246 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7836 ,  H01L29/792

Abstract: An apparatus includes a multiple time programmable (MTP) memory device. The MTP memory device includes a metal gate, a substrate material, and an oxide structure between the metal gate and the substrate material. The oxide structure includes a hafnium oxide layer and a silicon dioxide layer. The hafnium oxide layer is in contact with the metal gate and in contact with the silicon dioxide layer. The silicon dioxide layer is in contact with the substrate material. The MTP device includes a transistor, and a non-volatile state of the MTP memory device is based on a threshold voltage of the transistor.

Abstract translation: 一种装置包括多时间可编程（MTP）存储器件。 MTP存储器件包括金属栅极，衬底材料和金属栅极和衬底材料之间的氧化物结构。 氧化物结构包括氧化铪层和二氧化硅层。 氧化铪层与金属栅极接触并与二氧化硅层接触。 二氧化硅层与衬底材料接触。 MTP器件包括晶体管，并且MTP存储器件的非易失性状态基于晶体管的阈值电压。

公开(公告)号：US11581037B2

公开(公告)日：2023-02-14

申请号：US17341797

申请日：2021-06-08

Applicant: QUALCOMM Incorporated

Inventor： Xiaonan Chen ,  Zhongze Wang ,  Yandong Gao ,  Mustafa Badaroglu

IPC: G11C11/419 ,  G11C11/4094 ,  G06F7/544 ,  G11C11/4091 ,  G06N3/063 ,  G11C11/4097

Abstract: Digital compute-in-memory (DCIM) bit cell circuit layouts and DCIM array circuits for multiple operations per column are disclosed. A DCIM bit cell array circuit including DCIM bit cell circuits comprising exemplary DCIM bit cell circuit layouts disposed in columns is configured to evaluate the results of multiple multiply operations per clock cycle. The DCIM bit cell circuits in the DCIM bit cell circuit layouts each couples to one of a plurality of column output lines in a column. In this regard, in each cycle of a system clock, each of the plurality of column output lines receives a result of a multiply operation of a DCIM bit cell circuit coupled to the column output line. The DCIM bit cell array circuit includes digital sense amplifiers coupled to each of the plurality of column output lines to reliably evaluate a result of a plurality of multiply operations per cycle.

公开(公告)号：US10964380B1

公开(公告)日：2021-03-30

申请号：US16784149

申请日：2020-02-06

Applicant: QUALCOMM Incorporated

Inventor： Zhongze Wang ,  Yandong Gao ,  Xia Li ,  Ye Lu ,  Xiaochun Zhu ,  Xiaonan Chen

IPC: G11C11/41 ,  G11C11/412 ,  G11C11/56 ,  G11C11/419 ,  H01L27/11 ,  G11C11/418 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00

Abstract: A memory circuit that includes a memory bitcell. The memory bitcell includes a six-transistor circuit configuration, a first transistor coupled to the six-transistor circuit configuration, a second transistor coupled to the first transistor, a third transistor coupled to the second transistor, and a capacitor coupled to the second transistor and the third transistor. The memory circuit includes a read word line coupled to the third transistor, a read bit line coupled to the third transistor, and an activation line coupled to the second transistor. The memory bitcell may be configured to operate as a NAND memory bitcell. The memory bitcell may be configured to operate as a NOR memory bitcell.

公开(公告)号：US09576801B2

公开(公告)日：2017-02-21

申请号：US14556983

申请日：2014-12-01

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Jeffrey Junhao Xu ,  Zhongze Wang ,  Bin Yang ,  Xiaonan Chen ,  Yu Lu

IPC: H01L27/11 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L29/788 ,  H01L21/02 ,  G11C16/04

CPC classification number: H01L21/28088 ,  G11C16/0408 ,  H01L21/02148 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/28273 ,  H01L21/28291 ,  H01L29/4966 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7851 ,  H01L29/7883

Abstract: Non-volatile memory devices and logic devices are fabricated using processes compatible with high dielectric constant/metal gate (HK/MG) processes for increased cell density and larger scale integration. A doped oxide layer, such as a silicon-doped hafnium oxide (HfO2) layer, is implemented as a ferroelectric dipole layer in a nonvolatile memory device.

Abstract translation: 使用与高介电常数/金属栅（HK / MG）工艺兼容的工艺制造非易失性存储器件和逻辑器件，用于增加电池密度和更大规模的集成。 掺杂氧化物层，例如掺杂硅的氧化铪（HfO 2）层，在非易失性存储器件中被实现为铁电偶极子层。

公开(公告)号：US09413349B1

公开(公告)日：2016-08-09

申请号：US14676228

申请日：2015-04-01

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Xiao Lu ,  Xiaonan Chen ,  Zhongze Wang ,  Choh Fei Yeap

IPC: G11C16/10 ,  H03K17/687 ,  H01L29/792 ,  H01L29/51 ,  H01L27/115 ,  G11C16/04

CPC classification number: H03K17/687 ,  G11C16/0466 ,  G11C16/10 ,  H01L27/1052 ,  H01L27/11563 ,  H01L27/11568 ,  H01L29/51 ,  H01L29/792

Abstract: Aspects disclosed in the detailed description include high-k (HK)/metal gate (MG) (HK/MG) multi-time programmable (MTP) switching devices, and related systems and methods. One type of HK/MG MTP switching device is an MTP metal-oxide semiconductor (MOS) field-effect transistor (MOSFET). When the MTP MOSFET is programmed, a charge trap may build up in the MTP MOSFET due to a switching electrical current induced by a switching voltage. The charge trap reduces the switching window and endurance of the MTP MOSFET, thus reducing reliability in accessing the information stored in the MTP MOSFET. In this regard, an HK/MG MTP switching device comprising the MTP MOSFET is configured to eliminate the switching electrical current when the MTP MOSFET is programmed. By eliminating the switching electrical current, it is possible to avoid a charge trap in the MTP MOSFET, thus restoring the switching window and endurance of the MTP MOSFET for reliable information access.

Abstract translation: 在详细描述中公开的方面包括高k（HK）/金属门（MG）（HK / MG）多时间可编程（MTP）交换设备以及相关的系统和方法。 一种类型的HK / MG MTP开关器件是MTP金属氧化物半导体（MOS）场效应晶体管（MOSFET）。 当编程MTP MOSFET时，由于开关电压引起的开关电流，电荷陷阱可能会积累在MTP MOSFET中。 电荷阱减少了MTP MOSFET的开关窗口和耐久性，从而降低了访问存储在MTP MOSFET中的信息的可靠性。 在这方面，包括MTP MOSFET的HK / MG MTP开关器件被配置为在编程MTP MOSFET时消除开关电流。 通过消除开关电流，可以避免MTP MOSFET中的电荷陷阱，从而恢复MTP MOSFET的开关窗口和耐用性，从而实现可靠的信息访问。

公开(公告)号：US11626156B2

公开(公告)日：2023-04-11

申请号：US17404378

申请日：2021-08-17

Applicant: QUALCOMM Incorporated

Inventor： Xiaonan Chen ,  Zhongze Wang

IPC: G11C7/12 ,  G11C11/413 ,  G11C11/54 ,  G11C7/10 ,  G11C11/419

Abstract: Compute-in-memory (CIM) bit cell array circuits include CIM bit cell circuits for multiply-accumulate operations. The CIM bit cell circuits include a memory bit cell circuit for storing a weight data in true and complement form. The CIM bit cell circuits include a true pass-gate circuit and a complement pass-gate circuit for generating a binary product of the weight data and an activation input on a product node. An RWL circuit couples the product node to a ground voltage for initialization. The CIM bit cell circuits also include a plurality of consecutive gates each coupled to at least one of the memory bit cell circuit, the true pass-gate circuit, the complement pass-gate circuit, and the RWL circuit. Each of the CIM bit cell circuits in the CIM bit cell array circuit is disposed in an orientation of a CIM bit cell circuit layout including the RWL circuit.

公开(公告)号：US20160247554A1

公开(公告)日：2016-08-25

申请号：US14631603

申请日：2015-02-25

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Zhongze Wang ,  Xiaonan Chen ,  Stanley Seungchul Song ,  Choh Fei Yeap

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C7/20 ,  G11C11/417 ,  G11C29/021 ,  G11C29/028 ,  G11C29/24 ,  G11C29/50 ,  G11C29/50004 ,  G11C2029/0407 ,  G11C2029/0409 ,  G11C2029/5002

Abstract: An apparatus includes a static random-access memory and circuitry configured to initiate a corrective action associated with the static random-access memory. The corrective action may be initiated based on a number of static random-access memory cells that have a particular state responsive to a power-up of the static random-access memory.

Abstract translation: 一种装置包括静态随机存取存储器和被配置为发起与静态随机存取存储器相关联的校正动作的电路。 可以基于具有响应于静态随机存取存储器的加电的特定状态的多个静态随机存取存储器单元来启动校正动作。

公开(公告)号：US11631455B2

公开(公告)日：2023-04-18

申请号：US17152564

申请日：2021-01-19

Applicant: QUALCOMM Incorporated

Inventor： Seyed Arash Mirhaj ,  Xiaonan Chen ,  Ankit Srivastava ,  Sameer Wadhwa ,  Zhongze Wang

IPC: G11C11/419 ,  G06F7/544

Abstract: A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate for multiplying the stored bit with an input vector bit. An output node for the logic gate connects to a second plate of a capacitor. A first plate of the capacitor connects to a read bit line. A write driver controls a power supply voltage to the cross-coupled inverters, the first switch, and the second switch to capacitively write the stored bit to the pair of cross-coupled inverters.