公开(公告)号：US11830776B2

公开(公告)日：2023-11-28

申请号：US17730691

申请日：2022-04-27

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Jean Jimenez Martinez

IPC: H01L21/82 ,  H01L21/8248 ,  H01L27/06 ,  H01L29/06 ,  H01L29/66 ,  H01L29/808 ,  H01L29/423 ,  H10B20/00 ,  H01L21/62 ,  H01L21/04

CPC classification number: H01L21/8248 ,  H01L21/046 ,  H01L21/0415 ,  H01L21/62 ,  H01L27/0623 ,  H01L29/0653 ,  H01L29/42376 ,  H01L29/66893 ,  H01L29/808 ,  H10B20/40

Abstract: An integrated circuit includes a junction field-effect transistor formed in a semiconductor substrate. The junction field-effect transistor includes a drain region, a source region, a channel region, and a gate region. A first isolating region separates the drain region from both the gate region and the channel region. A first connection region connects the drain region to the channel region by passing underneath the first isolating region in the semiconductor substrate. A second isolating region separates the source region from both the gate region and the channel region. A second connection region connects the source region to the channel region by passing underneath the second isolating region in the semiconductor substrate.

公开(公告)号：US11784058B2

公开(公告)日：2023-10-10

申请号：US17391345

申请日：2021-08-02

Applicant: Micron Technology, Inc.

Inventor： Eric Freeman ,  Paolo Tessariol

IPC: H01L21/311 ,  H01L23/522 ,  H01L23/64 ,  H01L21/62 ,  H01L49/02 ,  H10B43/27

CPC classification number: H01L21/31111 ,  H01L23/5223 ,  H01L28/60 ,  H01L28/86 ,  H01L28/90 ,  H10B43/27

Abstract: Some embodiments include an integrated structure having a semiconductor base and an insulative frame over the semiconductor base. The insulative frame has vertically-spaced sheets of first insulative material, and pillars of second insulative material between the vertically-spaced sheets. The first and second insulative materials are different from one another. Conductive plates are between the vertically-spaced sheets and are directly against the insulative pillars. Some embodiments include capacitors, and some embodiments include methods of forming capacitors.

公开(公告)号：US10784365B2

公开(公告)日：2020-09-22

申请号：US16264955

申请日：2019-02-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Veeraraghavan S. Basker ,  Zuoguang Liu ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/40 ,  H01L21/311 ,  H01L21/62 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/3065 ,  H01L21/265 ,  H01L21/02 ,  H01L29/08 ,  H01L27/088

Abstract: A method of forming a fin field effect transistor (finFET), including forming a temporary gate structure having a sacrificial gate layer and a dummy gate layer on the sacrificial gate layer, forming a gate spacer layer on each sidewall of the temporary gate structure, forming a source/drain spacer layer on the outward-facing sidewall of each gate spacer layer, removing the dummy gate layer to expose the sacrificial gate layer, removing the sacrificial gate layer to form a plurality of recessed cavities, and forming a gate structure, where the gate structure occupies at least a portion of the plurality of recessed cavities.

公开(公告)号：US10283507B2

公开(公告)日：2019-05-07

申请号：US15586285

申请日：2017-05-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung

IPC: H01L21/62 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L21/02 ,  H01L29/10

Abstract: A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; a first bump on the first region; a first doped layer on the first fin-shaped structure and the bump; and a gate structure covering the bump.

公开(公告)号：US09972671B2

公开(公告)日：2018-05-15

申请号：US15132758

申请日：2016-04-19

Applicant: International Business Machines Corporation

Inventor： Daniel C. Edelstein ,  Chih-Chao Yang

IPC: H01L49/02 ,  H01L21/02 ,  H01L21/62 ,  H01L27/01 ,  H01L23/522

CPC classification number: H01L28/24 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/62 ,  H01L23/5228 ,  H01L27/016

Abstract: A semiconductor structure is provided that includes a first metal resistor structure located on a portion of a dielectric-containing substrate. The first metal resistor structure includes, from bottom to top, a first nitridized dielectric surface layer portion having a first nitrogen content, a first metal portion, and a first dielectric capping layer portion. The semiconductor structure of the present application further includes a second metal resistor structure located on a second portion of the dielectric-containing substrate and spaced apart from the first metal resistor structure. The second metal resistor structure includes, from bottom to top, a second nitridized dielectric surface layer portion having a second nitrogen content that differs from the first nitrogen content, a second metal portion, and a second dielectric capping layer portion.

公开(公告)号：US09780200B2

公开(公告)日：2017-10-03

申请号：US14411073

申请日：2014-01-16

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu

IPC: H01L29/66 ,  H01L21/62 ,  H01L29/78 ,  H01L21/762

CPC classification number: H01L29/6681 ,  H01L21/26506 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor arrangement and a method for manufacturing the same. An arrangement may include a bulk semiconductor substrate; a fin formed on the substrate; a first FinFET and a second FinFET formed on the substrate. The first FinFET comprises a first gate stack intersecting the fin and a first gate spacer disposed on sidewalls of the first gate stack. The second FinFET includes a second gate stack intersecting the fin and a second gate spacer disposed on sidewalls of the second gate stack; a dummy gate spacer formed between the first FinFET and the second FinFET and intersecting the fin; an isolation section self-aligned to a space defined by the dummy gate spacer. The isolation section electrically isolates the first FinFET from the second FinFET; and an insulation layer disposed under and abutting the isolation section.

公开(公告)号：US09669416B2

公开(公告)日：2017-06-06

申请号：US13918742

申请日：2013-06-14

Applicant: Massachusetts Institute of Technology

Inventor： Luis Fernando Velásquez-García ,  Frances Ann Hill ,  Philip James Ponce De Leon

IPC: B05B1/14 ,  B05D1/04 ,  H01L21/62 ,  B05B5/025 ,  B05D1/00 ,  D01D5/00 ,  B82Y30/00 ,  B05B5/053

CPC classification number: B05B5/0255 ,  B05B1/14 ,  B05B5/025 ,  B05B5/0536 ,  B05D1/007 ,  B82Y30/00 ,  D01D5/0069

Abstract: Electrospraying systems and associated methods are generally described.

公开(公告)号：US09423377B2

公开(公告)日：2016-08-23

申请号：US14945211

申请日：2015-11-18

Applicant: Robert Bosch GmbH

Inventor： Robert Roelver ,  Daniel Pantel ,  Stefan Henneck

IPC: H01L21/00 ,  G01N27/416 ,  G01N27/407 ,  H01L21/62 ,  G01N27/414

CPC classification number: G01N27/4166 ,  G01N27/407 ,  G01N27/4071 ,  G01N27/4077 ,  G01N27/4143 ,  H01L21/62

Abstract: A device for detecting at least one gaseous analyte comprises a detection section including a semiconductor substrate and at least one sensor element, which is arranged on the semiconductor substrate. The at least one sensor element includes two electrodes and a solid electrolyte layer arranged between the electrodes. The device also comprises a protective cap configured to cover the at least one sensor element, and at least one temperature-control unit configured for temperature control of the protective cap. The at least one temperature-control unit is arranged on the protective cap. The protective cap is formed from a semiconductor material. The device further comprises a diffusion section having a plurality of passage openings for the gaseous analyte arranged at least in a partial section of the protective cap.

Abstract translation: 用于检测至少一种气态分析物的装置包括检测部分，其包括半导体衬底和布置在半导体衬底上的至少一个传感器元件。 所述至少一个传感器元件包括两个电极和布置在所述电极之间的固体电解质层。 该装置还包括构造成覆盖至少一个传感器元件的保护盖，以及被配置用于保护盖的温度控制的至少一个温度控制单元。 至少一个温度控制单元设置在保护盖上。 保护盖由半导体材料形成。 该装置还包括扩散部分，该扩散部分具有多个用于气体分析器的通道开口，该通气开口至少布置在保护帽的部分部分中。

公开(公告)号：US20140021439A1

公开(公告)日：2014-01-23

申请号：US13551873

申请日：2012-07-18

Applicant: Fabio Pellizzer ,  Cinzia Perrone

Inventor： Fabio Pellizzer ,  Cinzia Perrone

IPC: H01L27/24 ,  H01L21/62 ,  H01L45/00 ,  H01L21/768

CPC classification number: H01L21/31111 ,  H01L21/02115 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1675

Abstract: Some embodiments include methods of forming semiconductor constructions. Carbon-containing material is formed over oxygen-sensitive material. The carbon-containing material and oxygen-sensitive material together form a structure having a sidewall that extends along both the carbon-containing material and the oxygen-sensitive material. First protective material is formed along the sidewall. The first protective material extends across an interface of the carbon-containing material and the oxygen-sensitive material, and does not extend to a top region of the carbon-containing material. Second protective material is formed across the top of the carbon-containing material, with the second protective material having a common composition to the first protective material. The second protective material is etched to expose an upper surface of the carbon-containing material. Some embodiments include semiconductor constructions, memory arrays and methods of forming memory arrays.

公开(公告)号：US08574954B2

公开(公告)日：2013-11-05

申请号：US12872945

申请日：2010-08-31

Applicant: Sanh D. Tang

Inventor： Sanh D. Tang

IPC: H01L21/62

CPC classification number: H01L45/1253 ,  G11C13/0004 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1675 ,  H01L45/1683

Abstract: Methods, devices, and systems associated with phase change material memory are described herein. In one or more embodiments, a method of forming a phase change material memory cell includes forming a number of memory structure regions, wherein the memory structure regions include a bottom electrode material and a sacrificial material, forming a number of insulator regions between the number of memory structure regions, forming a number of openings between the number of insulator regions and forming a contoured surface on the number of insulator regions by removing the sacrificial material and a portion of the number of insulator regions, forming a number of dielectric spacers on the number of insulator regions, forming a contoured opening between the number of insulator regions and exposing the bottom electrode material by removing a portion of the number of dielectric spacers, and forming a phase change material in the opening between the number of insulator regions.

Abstract translation: 本文描述了与相变材料存储器相关联的方法，装置和系统。 在一个或多个实施例中，形成相变材料存储单元的方法包括形成多个存储器结构区域，其中存储器结构区域包括底部电极材料和牺牲材料，在多个绝缘体区域之间形成多个绝缘体区域 存储器结构区域，在多个绝缘体区域之间形成多个开口，并通过去除牺牲材料和绝缘体区域的数量的一部分在绝缘体区域的数量上形成轮廓表面，在数量上形成多个电介质间隔物 的绝缘体区域之间，在多个绝缘体区域之间形成轮廓的开口，并通过去除一部分电介质间隔物而露出底部电极材料，并且在绝缘体区域之间的开口中形成相变材料。