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公开(公告)号：US20230397330A1
公开(公告)日：2023-12-07
申请号：US17901402
申请日：2022-09-01
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor： Seong Ho Choi , Seong II Jeon
CPC classification number: H05K1/0298 , H05K1/115 , H05K2201/0275 , H05K2201/09554
Abstract: A printed circuit board includes an insulating layer, and a first wiring layer at least partially embedded in one surface of the insulating layer, one surface of the first wiring layer being exposed from the one surface of the insulating layer. The insulating layer includes a first insulating layer covering at least a portion of a side surface of the first wiring layer, and a second insulating layer disposed on the first insulating layer and the first wiring layer, and the first and second insulating layers include different insulating materials.
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公开(公告)号：US09743523B2
公开(公告)日：2017-08-22
申请号：US14512514
申请日：2014-10-13
Applicant: TRIPOD TECHNOLOGY CORPORATION
Inventor： Bo-Shiung Huang , Wei-Hsiung Yang , Han-Ching Shih , Cheng-Feng Lin
IPC: H05K1/03 , H05K1/18 , H01F27/28 , H01F41/04 , H05K3/46 , H05K1/11 , H05K3/42 , H01F17/00 , H01F17/06 , H05K1/16 , H05K3/00 , H05K1/02
CPC classification number: H05K1/181 , H01F17/0006 , H01F17/06 , H01F27/2804 , H01F41/046 , H05K1/0272 , H05K1/0366 , H05K1/115 , H05K1/165 , H05K3/0044 , H05K3/0052 , H05K3/427 , H05K3/4602 , H05K3/4655 , H05K3/4697 , H05K2201/0187 , H05K2201/0275 , H05K2201/086 , H05K2201/09036 , H05K2201/1003 , H05K2203/1178 , Y10T29/302 , Y10T29/49165
Abstract: A printed circuit board package structure includes a substrate, plural ring-shaped magnetic elements, a support layer, and first conductive layers. The substrate has two opposite first and second surfaces, first ring-shaped recesses, and first grooves. Each of the first ring-shaped recesses is communicated with another first ring-shaped recess through at least one of the first grooves, and at least two of the first ring-shaped recesses are communicated with a side surface of the substrate through the first grooves to form at least two openings. The ring-shaped magnetic elements are respectively located in the first ring-shaped recesses. The support layer is located on the first surface, and covers the first ring-shaped recesses and the first grooves. The support layer and the substrate have through holes. The first conductive layers are respectively located on surfaces of support layer and substrate facing the through holes.
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公开(公告)号：US09635762B2
公开(公告)日：2017-04-25
申请号：US14803889
申请日：2015-07-20
Applicant: J-DEVICES CORPORATION
Inventor： Shinji Watanabe , Sumikazu Hosoyamada , Shingo Nakamura , Hiroshi Demachi , Takeshi Miyakoshi , Tomoshige Chikai , Kiminori Ishido , Hiroaki Matsubara , Takashi Nakamura , Hirokazu Honda , Yoshikazu Kumagaya , Shotaro Sakumoto , Toshihiro Iwasaki , Michiaki Tamakawa
IPC: H01L23/02 , H01L23/10 , H05K1/18 , H01L23/367 , H05K1/02 , H01L25/10 , H01L23/36 , H01L23/373 , H01L23/433 , H01L23/498 , H01L23/31
CPC classification number: H05K1/181 , H01L23/3128 , H01L23/36 , H01L23/3675 , H01L23/3677 , H01L23/3733 , H01L23/4334 , H01L23/49816 , H01L25/105 , H01L2224/16227 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2225/1094 , H01L2924/15331 , H01L2924/1815 , H05K1/0204 , H05K1/0206 , H05K1/0209 , H05K1/141 , H05K2201/0275 , H05K2201/066 , H05K2201/10515 , H05K2203/1311 , H05K2203/1322 , H01L2924/00012 , H01L2924/00
Abstract: A stacked semiconductor package includes a first semiconductor package including a first circuit board and a first semiconductor device mounted on the first circuit board; a second semiconductor package including a second circuit board and a second semiconductor device mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package; and a heat transfer member provided on the first semiconductor device and a part of the first circuit board, the part being around the first semiconductor device.
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公开(公告)号：US20230397333A1
公开(公告)日：2023-12-07
申请号：US17833568
申请日：2022-06-06
Applicant: Intel Corporation
Inventor： Eng Huat GOH , Chee Kheong YOON , Telesphor KAMGAING , Jooi Wah WONG , Min Suet LIM , Kavitha NAGARAJAN , Chan Kim LEE , Chu Aun LIM
CPC classification number: H05K1/115 , H05K3/429 , H05K3/4644 , H05K2201/09827 , H05K2201/0275 , H05K2203/107 , H05K2203/02 , H05K2201/09854
Abstract: Embodiments disclosed herein include package substrates. In an embodiment, the package substrate comprises a core. In an embodiment, the core comprises a first sub-core layer and a second sub-core layer. In an embodiment, a via is provided through the first sub-core layer and the second sub-core layer. In an embodiment, the via comprises a first hourglass shape in the first sub-core layer and a second hourglass shape in the second sub-core layer. In an embodiment, a front-side buildup layer is over the core and a backside buildup layer is under the core.
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5.发明授权公开(公告)号：US09639189B2
公开(公告)日：2017-05-02
申请号：US14732817
申请日：2015-06-08
Applicant: Hitachi Chemical Company, Ltd.
Inventor： Hiroshi Yamazaki , Yoshimi Igarashi
IPC: G06F3/047 , H05K1/03 , G06F3/041 , H05K3/06 , G03F7/027 , G03F7/09 , G03F7/095 , G03F7/20 , G03F7/00 , H05K1/02 , H05K1/09
CPC classification number: G06F3/041 , G03F7/0005 , G03F7/027 , G03F7/09 , G03F7/092 , G03F7/095 , G03F7/0952 , G03F7/0955 , G03F7/2022 , G06F3/044 , G06F2203/04112 , H05K1/0274 , H05K1/0313 , H05K1/036 , H05K1/09 , H05K3/06 , H05K2201/0275 , Y10T428/24802
Abstract: A conductive pattern formation method of the present invention includes a first exposure step of radiating active light in a patterned manner to a photosensitive layer including a photosensitive resin layer provided on a substrate and a conductive film provided on a surface of the photosensitive resin layer on a side opposite to the substrate; a second exposure step of radiating active light, in the presence of oxygen, to some or all of the portions of the photosensitive layer not exposed at least in the first exposure step; and a development step of developing the photosensitive layer to form a conductive pattern following the second exposure step.
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Patent Agency Ranking
公开(公告)号：US20160027715A1
公开(公告)日：2016-01-28
申请号：US14803889
申请日：2015-07-20
Applicant: J-DEVICES CORPORATION
Inventor： Shinji WATANABE , Sumikazu HOSOYAMADA , Shingo NAKAMURA , Hiroshi DEMACHI , Takeshi MIYAKOSHI , Tomoshige CHIKAI , Kiminori ISHIDO , Hiroaki MATSUBARA , Takashi NAKAMURA , Hirokazu HONDA , Yoshikazu KUMAGAYA , Shotaro SAKUMOTO , Toshihiro IWASAKI , Michiaki TAMAKAWA
IPC: H01L23/373 , H05K1/18 , H01L23/31 , H05K1/02 , H01L25/065 , H01L23/367
CPC classification number: H05K1/181 , H01L23/3128 , H01L23/36 , H01L23/3675 , H01L23/3677 , H01L23/3733 , H01L23/4334 , H01L23/49816 , H01L25/105 , H01L2224/16227 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2225/1094 , H01L2924/15331 , H01L2924/1815 , H05K1/0204 , H05K1/0206 , H05K1/0209 , H05K1/141 , H05K2201/0275 , H05K2201/066 , H05K2201/10515 , H05K2203/1311 , H05K2203/1322 , H01L2924/00012 , H01L2924/00
Abstract: A stacked semiconductor package includes a first semiconductor package including a first circuit board and a first semiconductor device mounted on the first circuit board; a second semiconductor package including a second circuit board and a second semiconductor device mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package; and a heat transfer member provided on the first semiconductor device and a part of the first circuit board, the part being around the first semiconductor device.
Abstract translation: 叠层半导体封装包括：第一半导体封装，包括第一电路板和安装在第一电路板上的第一半导体器件; 第二半导体封装，包括第二电路板和安装在第二电路板上的第二半导体器件，第二半导体封装堆叠在第一半导体封装上; 以及设置在第一半导体器件上的传热部件和第一电路板的一部分，该部分围绕第一半导体器件。
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公开(公告)号：US09169346B2
公开(公告)日：2015-10-27
申请号：US12337651
申请日：2008-12-18
Applicant: Chien-Jen Chung , Zhuo Wang
Inventor： Chien-Jen Chung , Zhuo Wang
IPC: C08G59/30 , B32B15/14 , B32B27/04 , B32B27/18 , B32B27/38 , C08J5/24 , C08L63/00 , B32B17/04 , H05K1/03 , B32B27/26 , B32B17/10 , C08K3/36
CPC classification number: C08G59/30 , B32B15/14 , B32B17/04 , B32B17/10733 , B32B27/04 , B32B27/18 , B32B27/26 , B32B27/38 , C08G59/308 , C08J5/24 , C08J2363/00 , C08J2363/02 , C08J2463/02 , C08K3/36 , C08K2201/019 , C08L63/00 , C08L2205/16 , C08L2666/58 , H05K1/0366 , H05K1/0373 , H05K2201/0209 , H05K2201/0239 , H05K2201/0275 , Y10T428/259 , Y10T428/2971 , Y10T428/31529 , C08L2666/54
Abstract: Provided herein are, among other things, epoxy resin varnishes and methods of making and using the same. In some embodiments, the epoxy resin varnishes comprise at least a filler such as silica. In certain embodiments, the epoxy resin varnishes provided herein are used for making laminates such as copper clad laminates. In farther embodiments, the copper clad laminates provided herein are used for making printed circuit boards (PCBs).
Abstract translation: 除此之外，本文提供环氧树脂清漆及其制备和使用方法。 在一些实施方案中，环氧树脂清漆至少包含填料如二氧化硅。 在某些实施方案中，本文提供的环氧树脂清漆用于制造层压体，例如覆铜层压板。 在更远的实施例中，本文提供的覆铜层压板用于制造印刷电路板（PCB）。
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8.发明授权公开(公告)号：US09105616B2
公开(公告)日：2015-08-11
申请号：US14142719
申请日：2013-12-27
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor： Chang Seob Hong , Eun Jung Jo , Kyu Hwan Oh , Kang Hyun Lee
IPC: H01L23/48 , H01L23/482 , H01L23/00
CPC classification number: H01L23/482 , H01L23/295 , H01L23/49811 , H01L24/16 , H01L24/29 , H01L25/0652 , H01L25/0655 , H01L25/16 , H01L2224/16225 , H01L2224/81447 , H01L2924/01322 , H01L2924/12042 , H01L2924/1531 , H01L2924/181 , H01L2924/19106 , H05K1/0366 , H05K1/141 , H05K3/181 , H05K2201/0275 , H05K2201/049 , H01L2924/00 , H01L2924/00014
Abstract: Disclosed herein are an external connection terminal part, a semiconductor package having the external connection terminal part, and a method for manufacturing the same. According to a preferred embodiment of the present invention, the external connection terminal part includes an insulating material and metal plating pattern formed on both surfaces of the insulating material.
Abstract translation: 这里公开了一种外部连接端子部件，具有外部连接端子部件的半导体封装件及其制造方法。 根据本发明的优选实施例，外部连接端子部分包括形成在绝缘材料的两个表面上的绝缘材料和金属电镀图案。
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9.发明申请公开(公告)号：US20150036309A1
公开(公告)日：2015-02-05
申请号：US14444583
申请日：2014-07-28
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor： Jean-Michel Riviere , Karine Saxod
CPC classification number: H05K1/0271 , H01L23/49844 , H01L23/562 , H01L24/16 , H01L2224/131 , H01L2224/16111 , H01L2224/16237 , H05K1/181 , H05K3/28 , H05K3/30 , H05K2201/0275 , H05K2201/09909 , H05K2201/10007 , H05K2201/2009 , Y10T29/4913 , H01L2924/014
Abstract: A substrate board includes an electrical connection network on a face thereof. An integrated-circuit chip is mounted to the face of the substrate board in electrical contact with the electrical connection network. A local reinforcing or balancing layer made of a non-metallic material is mounted to the face of the substrate board in at least one local zone free of the face which is free of metal portions of the electrical connection network.
Abstract translation: 基板包括在其表面上的电连接网络。 集成电路芯片安装到与电连接网络电接触的基板的表面。 由非金属材料制成的局部增强或平衡层在至少一个不具有电连接网络的金属部分的表面的局部区域中安装到基板的表面上。
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公开(公告)号：US20100092764A1
公开(公告)日：2010-04-15
申请号：US12337651
申请日：2008-12-18
Applicant: Chien-Jen CHUNG , Zhuo Wang
Inventor： Chien-Jen CHUNG , Zhuo Wang
CPC classification number: C08G59/30 , B32B15/14 , B32B17/04 , B32B17/10733 , B32B27/04 , B32B27/18 , B32B27/26 , B32B27/38 , C08G59/308 , C08J5/24 , C08J2363/00 , C08J2363/02 , C08J2463/02 , C08K3/36 , C08K2201/019 , C08L63/00 , C08L2205/16 , C08L2666/58 , H05K1/0366 , H05K1/0373 , H05K2201/0209 , H05K2201/0239 , H05K2201/0275 , Y10T428/259 , Y10T428/2971 , Y10T428/31529 , C08L2666/54
Abstract: Provided herein are, among other things, epoxy resin varnishes and methods of making and using the same. In some embodiments, the epoxy resin varnishes comprise at least a filler such as silica. In certain embodiments, the epoxy resin varnishes provided herein are used for making laminates such as copper clad laminates. In farther embodiments, the copper clad laminates provided herein are used for making printed circuit boards (PCBs).
Abstract translation: 除此之外，本文提供环氧树脂清漆及其制备和使用方法。 在一些实施方案中，环氧树脂清漆至少包含填料如二氧化硅。 在某些实施方案中，本文提供的环氧树脂清漆用于制造层压体，例如覆铜层压板。 在更远的实施例中，本文提供的覆铜层压板用于制造印刷电路板（PCB）。
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