公开(公告)号：US10256196B2

公开(公告)日：2019-04-09

申请号：US15198785

申请日：2016-06-30

Applicant: J-DEVICES CORPORATION

Inventor： Kiminori Ishido ,  Michiaki Tamakawa ,  Toshihiro Iwasaki

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31

Abstract: A semiconductor device in which an insulating material layer contains no reinforced fibers such as a glass cloth or a nonwoven cloth and which enables miniaturization of metal thin-film wiring layers, a reduction in the diameter of metal vias, and a reduction in interlayer thickness. The semiconductor device includes an insulating material layer including one or more semiconductor elements sealed with an insulating material containing no reinforced fibers, a plurality of metal thin-film wiring layers, metal vias that electrically connect the metal thin-film wiring layers together and electrodes of the semiconductor elements and the metal thin-film wiring layers together, and a warpage adjustment layer arranged on one principal surface of the insulating material layer to offset warpage of the insulating material layer to reduce warpage of the semiconductor device.

公开(公告)号：US09368474B2

公开(公告)日：2016-06-14

申请号：US14850589

申请日：2015-09-10

Applicant: J-DEVICES CORPORATION

Inventor： Hiroaki Matsubara ,  Tomoshige Chikai ,  Kiminori Ishido ,  Takashi Nakamura ,  Hirokazu Honda ,  Hiroshi Demachi ,  Yoshikazu Kumagaya ,  Shotaro Sakumoto ,  Shinji Watanabe ,  Sumikazu Hosoyamada ,  Shingo Nakamura ,  Takeshi Miyakoshi ,  Toshihiro Iwasaki ,  Michiaki Tamakawa

IPC: H01L23/00 ,  H01L25/065 ,  H01L21/78 ,  H01L21/56 ,  H01L21/304

CPC classification number: H01L24/96 ,  H01L21/3043 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/2518 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/8203 ,  H01L2224/92124 ,  H01L2224/92224 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2224/03 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A manufacturing method for a semiconductor device of the present invention includes: preparing a semiconductor wafer including an electrode formed therein; electrically connecting a first semiconductor element formed in a semiconductor chip and the electrode formed in the semiconductor wafer; filling a gap between the semiconductor wafer and the semiconductor chip with a first insulating resin layer; forming a second insulating resin layer on the semiconductor wafer; grinding the second insulating resin layer and the semiconductor chip until a thickness of the semiconductor chip reaches a predetermined thickness; forming a first insulating layer on the second insulating resin layer and the semiconductor chip; forming a line on the first insulating layer connected with a conductive material filled an opening in the first insulating layer and the second insulating resin layer to expose the electrode; and grinding the semiconductor wafer until a thickness of the semiconductor wafer reaches a predetermined thickness.

Abstract translation: 本发明的半导体装置的制造方法包括：准备包含形成在其中的电极的半导体晶片; 将形成在半导体芯片中的第一半导体元件和形成在半导体晶片中的电极电连接; 用第一绝缘树脂层填充半导体晶片和半导体芯片之间的间隙; 在半导体晶片上形成第二绝缘树脂层; 研磨第二绝缘树脂层和半导体芯片直到半导体芯片的厚度达到预定厚度; 在所述第二绝缘树脂层和所述半导体芯片上形成第一绝缘层; 在与填充有第一绝缘层和第二绝缘树脂层的开口的导电材料连接的第一绝缘层上形成线以露出电极; 并研磨半导体晶片直到半导体晶片的厚度达到预定厚度。

公开(公告)号：US09837382B2

公开(公告)日：2017-12-05

申请号：US15089630

申请日：2016-04-04

Applicant: J-DEVICES CORPORATION

Inventor： Shinji Watanabe ,  Toshihiro Iwasaki ,  Michiaki Tamakawa

IPC: H01L23/373 ,  H01L25/065 ,  H01L25/00 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L21/60 ,  H01L23/31 ,  H01L23/36 ,  H01L23/498

CPC classification number: H01L25/0655 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/49844 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L25/50 ,  H01L2021/60022 ,  H01L2224/04105 ,  H01L2224/16245 ,  H01L2224/2518 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/82005 ,  H01L2224/92224 ,  H01L2924/18162

Abstract: Thermal resistance is reduced from an element surface of a semiconductor chip to the rear surface of a semiconductor package. Split patterning of a metal is easily carried out, stress produced by a thermal expansion coefficient between silicon and metal is significantly reduced and environment reliability is improved. Low cost is realized by manufacturing a semiconductor package without using a TIM material. A semiconductor package is provided including a semiconductor chip including a first surface and a second surface opposed to the first surface and covered with a resin, an electrode being arranged over the first surface, a first wiring connected to the first surface directly or via a first opening arranged in the resin, and a second wiring connected to the second surface via a second opening arranged in the resin.

公开(公告)号：US09635762B2

公开(公告)日：2017-04-25

申请号：US14803889

申请日：2015-07-20

Applicant: J-DEVICES CORPORATION

Inventor： Shinji Watanabe ,  Sumikazu Hosoyamada ,  Shingo Nakamura ,  Hiroshi Demachi ,  Takeshi Miyakoshi ,  Tomoshige Chikai ,  Kiminori Ishido ,  Hiroaki Matsubara ,  Takashi Nakamura ,  Hirokazu Honda ,  Yoshikazu Kumagaya ,  Shotaro Sakumoto ,  Toshihiro Iwasaki ,  Michiaki Tamakawa

IPC: H01L23/02 ,  H01L23/10 ,  H05K1/18 ,  H01L23/367 ,  H05K1/02 ,  H01L25/10 ,  H01L23/36 ,  H01L23/373 ,  H01L23/433 ,  H01L23/498 ,  H01L23/31

CPC classification number: H05K1/181 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/3733 ,  H01L23/4334 ,  H01L23/49816 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15331 ,  H01L2924/1815 ,  H05K1/0204 ,  H05K1/0206 ,  H05K1/0209 ,  H05K1/141 ,  H05K2201/0275 ,  H05K2201/066 ,  H05K2201/10515 ,  H05K2203/1311 ,  H05K2203/1322 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A stacked semiconductor package includes a first semiconductor package including a first circuit board and a first semiconductor device mounted on the first circuit board; a second semiconductor package including a second circuit board and a second semiconductor device mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package; and a heat transfer member provided on the first semiconductor device and a part of the first circuit board, the part being around the first semiconductor device.

公开(公告)号：US09553052B2

公开(公告)日：2017-01-24

申请号：US14963970

申请日：2015-12-09

Applicant: J-DEVICES CORPORATION

Inventor： Hiroaki Matsubara ,  Toshihiro Iwasaki ,  Tomoshige Chikai ,  Kiminori Ishido ,  Shinji Watanabe ,  Michiaki Tamakawa

IPC: H01L29/82 ,  H01L23/552

CPC classification number: H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/15153 ,  H01L2224/83

Abstract: A magnetic shielding package of a non-volatile magnetic memory element, including: a soft magnetic material support plate 12; a first insulating material layer 13 formed on the support plate; a non-volatile magnetic memory element 11 fixed on the first insulating material layer; a second insulating material layer 14 that encapsulates the memory element and the periphery thereof; in the second insulating material layer, a wiring layer 15, a soft magnetic layer 15b or 25 and a conductive portion 16 connecting an electrode of the circuit surface of the memory element and the wiring layer; and a magnetic shield part 17 containing a soft magnetic material arranged like a wall at a distance from a side surface of the memory element so as to surround the memory element side surface partially or entirely, the magnetic shield part being magnetically connected to the soft magnetic layer.

Abstract translation: 一种非易失性磁存储元件的磁屏蔽封装，包括：软磁材料支撑板12; 形成在支撑板上的第一绝缘材料层13; 固定在第一绝缘材料层上的非易失性磁存储元件11; 封装存储元件及其周边的第二绝缘材料层14; 在第二绝缘材料层中，布线层15，软磁性层15b或25以及连接存储元件的电路表面的电极和布线层的导电部分16; 以及磁屏蔽部17，所述磁屏蔽部17包含与存储元件的侧面隔开一定距离地配置的软磁性材料，以便部分地或全部地包围存储元件侧表面，所述磁屏蔽部磁性地连接到软磁 层。

公开(公告)号：US20160079204A1

公开(公告)日：2016-03-17

申请号：US14850589

申请日：2015-09-10

Applicant: J-DEVICES CORPORATION

Inventor： Hiroaki Matsubara ,  Tomoshige Chikai ,  Kiminori Ishido ,  Takashi Nakamura ,  Hirokazu Honda ,  Hiroshi Demachi ,  Yoshikazu Kumagaya ,  Shotaro Sakumoto ,  Shinji Watanabe ,  Sumikazu Hosoyamada ,  Shingo Nakamura ,  Takeshi Miyakoshi ,  Toshihiro Iwasaki ,  Michiaki Tamakawa

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/304 ,  H01L21/78

CPC classification number: H01L24/96 ,  H01L21/3043 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/2518 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/8203 ,  H01L2224/92124 ,  H01L2224/92224 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2224/03 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A manufacturing method for a semiconductor device of the present invention includes: preparing a semiconductor wafer including an electrode formed therein; electrically connecting a first semiconductor element formed in a semiconductor chip and the electrode formed in the semiconductor wafer; filling a gap between the semiconductor wafer and the semiconductor chip with a first insulating resin layer; forming a second insulating resin layer on the semiconductor wafer; grinding the second insulating resin layer and the semiconductor chip until a thickness of the semiconductor chip reaches a predetermined thickness; forming a first insulating layer on the second insulating resin layer and the semiconductor chip; forming a line on the first insulating layer connected with a conductive material filled an opening in the first insulating layer and the second insulating resin layer to expose the electrode; and grinding the semiconductor wafer until a thickness of the semiconductor wafer reaches a predetermined thickness.

Abstract translation: 本发明的半导体装置的制造方法包括：准备包含形成在其中的电极的半导体晶片; 将形成在半导体芯片中的第一半导体元件和形成在半导体晶片中的电极电连接; 用第一绝缘树脂层填充半导体晶片和半导体芯片之间的间隙; 在半导体晶片上形成第二绝缘树脂层; 研磨第二绝缘树脂层和半导体芯片直到半导体芯片的厚度达到预定厚度; 在所述第二绝缘树脂层和所述半导体芯片上形成第一绝缘层; 在与填充有第一绝缘层和第二绝缘树脂层的开口的导电材料连接的第一绝缘层上形成线以露出电极; 并研磨半导体晶片直到半导体晶片的厚度达到预定厚度。