公开(公告)号：US20230395493A1

公开(公告)日：2023-12-07

申请号：US17833608

申请日：2022-06-06

Applicant: Intel Corporation

Inventor： Jooi Wah WONG ,  Eng Huat GOH ,  Telesphor KAMGAING ,  Chee Kheong YOON ,  Min Suet LIM ,  Kavitha NAGARAJAN ,  Chu Aun LIM

IPC: H01L23/528 ,  G11C11/4093

CPC classification number: H01L23/5283 ,  G11C11/4093

Abstract: Embodiments disclosed herein include package substrates. In an embodiment, a package substrate comprises a core, a first layer on the core, where the first layer comprises a first plane, a second layer on the first layer, where the second layer comprises first traces and second traces arranged in an alternating pattern, a third layer on the second layer, where the third layer comprises third traces and fourth traces arranged in an alternating pattern, and a fourth layer over the third layer, where the fourth layer comprises a second plane.

公开(公告)号：US20230420384A1

公开(公告)日：2023-12-28

申请号：US17848639

申请日：2022-06-24

Applicant: Intel Corporation

Inventor： Kavitha NAGARAJAN ,  Eng Huat GOH ,  Min Suet LIM ,  Telesphor KAMGAING ,  Chee Kheong YOON ,  Jooi Wah WONG ,  Chu Aun LIM

IPC: H01L23/552 ,  H01L23/367 ,  H01L23/16 ,  H01L23/00

CPC classification number: H01L23/552 ,  H01L23/367 ,  H01L23/16 ,  H01L23/562

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to a stiffener for a surface of a semiconductor package, where the stiffener includes slots that allow a gasket to go over the stiffener to electrically couple with a ground or a VSS of the semiconductor package. In embodiments, the gasket may include a material that blocks or absorbs EMI or RFI. Other embodiments may be described and/or claimed.

公开(公告)号：US20230395578A1

公开(公告)日：2023-12-07

申请号：US17833600

申请日：2022-06-06

Applicant: Intel Corporation

Inventor： Min Suet LIM ,  Kavitha NAGARAJAN ,  Eng Huat GOH ,  Telesphor KAMGAING ,  Chee Kheong YOON ,  Jooi Wah WONG ,  Chu Aun LIM

IPC: H01L25/10 ,  H01L25/065 ,  H01L23/538

CPC classification number: H01L25/105 ,  H01L25/0657 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2225/1058 ,  H01L2225/1035

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, and a base coupled to the package substrate. In an embodiment, a die is coupled to the base, and a memory die module is over the die. In an embodiment, the memory die module is communicatively coupled to the die through routing provided on the base

公开(公告)号：US20230395524A1

公开(公告)日：2023-12-07

申请号：US17833580

申请日：2022-06-06

Applicant: Intel Corporation

Inventor： Eng Huat GOH ,  Jiun Hann SIR ,  Chee Kheong YOON ,  Telesphor KAMGAING ,  Min Suet LIM ,  Kavitha NAGARAJAN ,  Chu Aun LIM

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/66 ,  H01L23/498

CPC classification number: H01L23/552 ,  H01L24/32 ,  H01L24/29 ,  H01L23/66 ,  H01L24/27 ,  H01L24/16 ,  H01L24/73 ,  H01L23/49822 ,  H01L2224/27515 ,  H01L2224/32227 ,  H01L2224/73204 ,  H01L2224/16235 ,  H01L2224/26155 ,  H01L2224/26175 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L2924/3511 ,  H01L2924/3025 ,  H01L2924/2027 ,  H01L2924/1421 ,  H01L2224/32237 ,  H01L2224/29018 ,  H01L2224/29078 ,  H01L2224/2919 ,  H01L2924/0781

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, and a die coupled to the package substrate. In an embodiment, a stiffener is around the die and over the package substrate. In an embodiment, an electrically non-conductive underfill is around first level interconnects (FLIs) between the package substrate and the die. In an embodiment, an electrically conductive layer is around the non-conductive underfill.

公开(公告)号：US20250054819A1

公开(公告)日：2025-02-13

申请号：US18447314

申请日：2023-08-10

Applicant: Intel Corporation

Inventor： Seok Ling LIM ,  Eng Huat GOH ,  Kavitha NAGARAJAN ,  Kang Eu ONG ,  Min Suet LIM

IPC: H01L23/053 ,  H01L21/48 ,  H01L23/16 ,  H01L23/544 ,  H01L25/065

Abstract: According to various aspects, there may be provided a stiffener assembly. The stiffener assembly may include a primary stiffener and an auxiliary stiffener. The primary stiffener may include a first engagement arrangement, and the auxiliary stiffener may include a second engagement arrangement. The first engagement arrangement of the primary stiffener and the second engagement arrangement of the auxiliary stiffener may be configured to form a detachable joint with each other, thereby enabling the auxiliary stiffener to be releasably connected to the primary stiffener for reinforcing the primary stiffener.

公开(公告)号：US20230420354A1

公开(公告)日：2023-12-28

申请号：US17848643

申请日：2022-06-24

Applicant: Intel Corporation

Inventor： Telesphor KAMGAING ,  Chee Kheong YOON ,  Chu Aun LIM ,  Eng Huat GOH ,  Min Suet LIM ,  Kavitha NAGARAJAN ,  Jooi Wah WONG

IPC: H01L23/498 ,  H01L21/48 ,  H05K1/18

CPC classification number: H01L23/49838 ,  H01L23/49816 ,  H01L23/49827 ,  H01L21/4853 ,  H05K1/181 ,  H01L23/49822 ,  H05K2201/10378 ,  H05K2201/10734

Abstract: Embodiments herein relate to systems, apparatuses, techniques, or processes directed to an electrical conductor, or power corridor, on the outside of a package substrate, wherein the electrical conductor is raised, or extends from a surface of the package substrate. In embodiments, this electrical conductor may be used to reduce the number of layers required within the package substrate by removing power planes within the substrate to the electrical conductors on the surface of the package. Other embodiments may be described and/or claimed.

公开(公告)号：US20230420350A1

公开(公告)日：2023-12-28

申请号：US17848630

申请日：2022-06-24

Applicant: Intel Corporation

Inventor： Kavitha NAGARAJAN ,  Eng Huat GOH ,  Min Suet LIM ,  Telesphor KAMGAING ,  Chee Kheong YOON ,  Jooi Wah WONG ,  Chu Aun LIM

IPC: H01L23/498 ,  H01L25/065 ,  H01L21/48

CPC classification number: H01L23/49833 ,  H01L25/0652 ,  H01L23/49816 ,  H01L24/16 ,  H01L23/49838 ,  H01L21/4853 ,  H01L23/49822

Abstract: Embodiments herein relate to systems, apparatuses, techniques or processes for packages that include a die complex with a base die that is coupled with a HDP substrate that in turn is coupled with an mSAP board. The HDP substrate may have a small trace width and trace spacing, for example three μm or less, that enable the HDP substrate to be used as a pitch translator between the base die and the mSAP board, for example between a 110 μm pitch and a 210 μm pitch. One or more DRAM modules may be coupled with the mSAP board. The configuration has a reduced overall package height. Other embodiments may be described and/or claimed.

公开(公告)号：US20230395577A1

公开(公告)日：2023-12-07

申请号：US17833592

申请日：2022-06-06

Applicant: Intel Corporation

Inventor： Eng Huat GOH ,  Telesphor KAMGAING ,  Jooi Wah WONG ,  Min Suet LIM ,  Chee Kheong YOON ,  Kavitha NAGARAJAN ,  Chu Aun LIM

IPC: H01L25/10 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06586

Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate with a cutout. In an embodiment, pads are adjacent to the cutout. In an embodiment, a memory die stack is on the package substrate, where the memory die stack is electrically coupled to the pads by routing in the package substrate. In an embodiment, a die is over the cutout, where the die is supported by the pads.

公开(公告)号：US20240332251A1

公开(公告)日：2024-10-03

申请号：US18129878

申请日：2023-04-02

Applicant: Intel Corporation

Inventor： Min Suet LIM ,  Kavitha NAGARAJAN ,  Stephan STOECKL ,  Eng Huat GOH

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/0652 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/3511 ,  H10B80/00

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a substrate with a first surface and a second surface opposite from the first surface. In an embodiment, a plurality of first dies are coupled to the first surface of the substrate, and a bump field is on the second surface of the substrate. In an embodiment, the bump field comprises a voided region towards a center of the substrate. In an embodiment, a second die is coupled to the second surface of the substrate, where the second die is provided in the voided region.

公开(公告)号：US20240006336A1

公开(公告)日：2024-01-04

申请号：US17852816

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Telesphor KAMGAING ,  Chu Aun LIM ,  Eng Huat GOH ,  Min Suet LIM ,  Kavitha NAGARAJAN ,  Jooi Wah WONG ,  Chee Kheong YOON

IPC: H01L23/552 ,  H01L23/538 ,  H01L21/48

CPC classification number: H01L23/552 ,  H01L23/5386 ,  H01L21/4846 ,  H01L24/16

Abstract: Embodiments herein relate to systems, apparatuses, techniques, or processes for stiffeners for a surface of a package substrate, where the stiffeners provide EMI/RFI shielding for signal traces or other electrical routings within the package, and in particular for traces at a surface of the package such as microstrip routings. Other embodiments may be described and/or claimed.