公开(公告)号：US20150371934A1

公开(公告)日：2015-12-24

申请号：US14744946

申请日：2015-06-19

Applicant: J-DEVICES CORPORATION

Inventor： Hirokazu HONDA ,  Shinji WATANABE ,  Toshihiro IWASAKI ,  Kiminori ISHIDO ,  Koichiro NIWA ,  Takeshi MIYAKOSHI ,  Sumikazu HOSOYAMADA ,  Yoshikazu KUMAGAYA ,  Tomoshige CHIKAI ,  Shingo NAKAMURA ,  Shotaro SAKUMOTO ,  Hiroaki MATSUBARA

IPC: H01L23/495 ,  H01L21/48

CPC classification number: H01L23/3675 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/4006 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/2518 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15151 ,  H01L2224/83

Abstract: A semiconductor package includes a support substrate arranged with a first aperture reaching a semiconductor device on a rear side, the semiconductor device is bonded via an adhesive to a surface of the support substrate, an insulating layer covering the semiconductor device, and wiring for connecting the semiconductor device and an external terminal through the insulating layer. The adhesive may form a part of the first aperture. In addition, a heat dissipation part may be arranged in the first aperture and a metal material may be filled in the first aperture.

Abstract translation: 一种半导体封装，包括布置有在后侧到达半导体器件的第一孔的支撑衬底，半导体器件通过粘合剂粘合到支撑衬底的表面，覆盖半导体器件的绝缘层和用于连接 半导体器件和通过绝缘层的外部端子。 粘合剂可以形成第一孔的一部分。 此外，可以在第一孔中布置散热部，并且可以在第一孔中填充金属材料。

公开(公告)号：US20150243576A1

公开(公告)日：2015-08-27

申请号：US14620854

申请日：2015-02-12

Applicant: J-DEVICES CORPORATION

Inventor： Takeshi MIYAKOSHI ,  Sumikazu HOSOYAMADA ,  Yoshikazu KUMAGAYA ,  Tomoshige CHIKAI ,  Shingo NAKAMURA ,  Hiroaki MATSUBARA

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495

CPC classification number: H01L23/3135 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/467 ,  H01L23/473 ,  H01L23/49524 ,  H01L23/49531 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/00 ,  H01L24/17 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L2224/16245 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40225 ,  H01L2224/73204 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/1203 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1304 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A semiconductor device includes a lead frame; a circuit board located on the lead frame; a power device that includes a switching element and is mounted on the circuit board via a bump located between the power device and the circuit board; and a heat releasing member connected to the power device. The circuit board may be a multi-layer wiring board. The circuit board may include a capacitor element, a resistor element, an inductor element, a diode element and a switching element.

Abstract translation: 半导体器件包括引线框架; 位于引线框架上的电路板; 功率器件，其包括开关元件，并且经由位于功率器件和电路板之间的凸块安装在电路板上; 以及与所述动力装置连接的散热构件。 电路板可以是多层布线板。 电路板可以包括电容器元件，电阻元件，电感器元件，二极管元件和开关元件。

公开(公告)号：US20170301599A1

公开(公告)日：2017-10-19

申请号：US15640071

申请日：2017-06-30

Applicant: J-DEVICES CORPORATION

Inventor： Takeshi MIYAKOSHI ,  Sumikazu HOSOYAMADA ,  Yoshikazu KUMAGAYA ,  Tomoshige CHIKAI ,  Shingo NAKAMURA ,  Hiroaki MATSUBARA ,  Shotaro SAKUMOTO

IPC: H01L23/31 ,  H01L23/467 ,  H01L23/473 ,  H01L23/495 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/3135 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/467 ,  H01L23/473 ,  H01L23/49524 ,  H01L23/49531 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/17 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L2224/16245 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40225 ,  H01L2224/73204 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/1203 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1304 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A semiconductor device includes a lead frame; a circuit board located on the lead frame; a power device that includes a switching element and is mounted on the circuit board via a bump located between the power device and the circuit board; and a heat releasing member connected to the power device. The circuit board may be a multi-layer wiring board. The circuit board may include a capacitor element, a resistor element, an inductor element, a diode element and a switching element.

公开(公告)号：US20170148766A1

公开(公告)日：2017-05-25

申请号：US15422981

申请日：2017-02-02

Applicant: J-DEVICES CORPORATION

Inventor： Takeshi MIYAKOSHI ,  Sumikazu HOSOYAMADA ,  Yoshikazu KUMAGAYA ,  Tomoshige CHIKAI ,  Shingo NAKAMURA ,  Hiroaki MATSUBARA ,  Shotaro SAKUMOTO

IPC: H01L25/065 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L21/486 ,  H01L23/3142 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/13013 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29191 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/20751 ,  H01L2924/01047 ,  H01L2924/00 ,  H01L2224/43

Abstract: A stacked semiconductor package in an embodiment includes a first semiconductor package including a first circuit board and a first semiconductor element mounted on the first circuit board; and a second semiconductor package including a second circuit board and a second semiconductor element mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package. The first semiconductor package further includes a sealing resin sealing the first semiconductor element; a conductive layer located in contact with the sealing resin; and a thermal via connected to the conductive layer and located on the first circuit board.

公开(公告)号：US20160172580A1

公开(公告)日：2016-06-16

申请号：US14963970

申请日：2015-12-09

Applicant: J-DEVICES CORPORATION

Inventor： Hiroaki MATSUBARA ,  Toshihiro IWASAKI ,  Tomoshige CHIKAI ,  Kiminori ISHIDO ,  Shinji WATANABE ,  Michiaki TAMAKAWA

IPC: H01L43/02 ,  H01L43/08

CPC classification number: H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/15153 ,  H01L2224/83

Abstract: A magnetic shielding package of a non-volatile magnetic memory element, including: a soft magnetic material support plate 12; a first insulating material layer 13 formed on the support plate; a non-volatile magnetic memory element 11 fixed on the first insulating material layer; a second insulating material layer 14 that encapsulates the memory element and the periphery thereof; in the second insulating material layer, a wiring layer 15, a soft magnetic layer 15b or 25 and a conductive portion 16 connecting an electrode of the circuit surface of the memory element and the wiring layer; and a magnetic shield part 17 containing a soft magnetic material arranged like a wall with a distance from a side surface of the memory element so as to surround the memory element side surface partially or entirely, the magnetic shield part being magnetically connected to the soft magnetic layer.

Abstract translation: 一种非易失性磁存储元件的磁屏蔽封装，包括：软磁材料支撑板12; 形成在支撑板上的第一绝缘材料层13; 固定在第一绝缘材料层上的非易失性磁存储元件11; 封装存储元件及其周边的第二绝缘材料层14; 在第二绝缘材料层中，布线层15，软磁性层15b或25以及连接存储元件的电路表面的电极和布线层的导电部分16; 以及磁屏蔽部17，所述磁屏蔽部17包含与所述存储元件的侧面间隔一定距离地形成为壁的软磁性材料，以便部分或全部地包围所述存储元件侧表面，所述磁屏蔽部磁性地连接到所述软磁 层。

公开(公告)号：US20150279759A1

公开(公告)日：2015-10-01

申请号：US14669491

申请日：2015-03-26

Applicant: J-DEVICES CORPORATION

Inventor： Takeshi Miyakoshi ,  Sumikazu HOSOYAMADA ,  Yoshikazu KUMAGAYA ,  Tomoshige CHIKAI ,  Shingo NAKAMURA ,  Hiroaki MATSUBARA ,  Shotaro SAKUMOTO

IPC: H01L23/367 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L25/0657 ,  H01L21/486 ,  H01L23/3142 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/13013 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29191 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/20751 ,  H01L2924/01047 ,  H01L2924/00 ,  H01L2224/43

Abstract: A stacked semiconductor package in an embodiment includes a first semiconductor package including a first circuit board and a first semiconductor element mounted on the first circuit board; and a second semiconductor package including a second circuit board and a second semiconductor element mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package. The first semiconductor package further includes a sealing resin sealing the first semiconductor element; a conductive layer located in contact with the sealing resin; and a thermal via connected to the conductive layer and located on the first circuit board.

Abstract translation: 实施例中的叠层半导体封装包括：第一半导体封装，包括第一电路板和安装在第一电路板上的第一半导体元件; 以及第二半导体封装，包括安装在第二电路板上的第二电路板和第二半导体元件，第二半导体封装堆叠在第一半导体封装上。 第一半导体封装还包括密封第一半导体元件的密封树脂; 与所述密封树脂接触的导电层; 以及连接到导电层并位于第一电路板上的热通孔。

公开(公告)号：US20170263560A1

公开(公告)日：2017-09-14

申请号：US15419091

申请日：2017-01-30

Applicant: J-Devices Corporation

Inventor： Hiroaki MATSUBARA ,  Tomoshige CHIKAI ,  Naoki HAYASHI ,  Toshihiro IWASAKI

IPC: H01L23/538 ,  H01L21/768

CPC classification number: H01L23/5384 ,  H01L21/486 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/2518 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244

Abstract: An object of the present invention is to provide an interconnect structure in which the current capacity of an interconnect pattern involving a large amount of current is increased without preventing miniaturization of signal lines and increasing film thickness. To accomplish this object, the present invention is configured as an interconnect structure including a resin layer; and interconnects formed on the resin layer, wherein the resin layer has a plurality of parallel grooves in an area in which the interconnects are formed, and the interconnects are formed of a plating film created on a resin layer front surface in the area, in which the interconnects are formed, and on inner wall surfaces of the plurality of grooves.

公开(公告)号：US20160027715A1

公开(公告)日：2016-01-28

申请号：US14803889

申请日：2015-07-20

Applicant: J-DEVICES CORPORATION

Inventor： Shinji WATANABE ,  Sumikazu HOSOYAMADA ,  Shingo NAKAMURA ,  Hiroshi DEMACHI ,  Takeshi MIYAKOSHI ,  Tomoshige CHIKAI ,  Kiminori ISHIDO ,  Hiroaki MATSUBARA ,  Takashi NAKAMURA ,  Hirokazu HONDA ,  Yoshikazu KUMAGAYA ,  Shotaro SAKUMOTO ,  Toshihiro IWASAKI ,  Michiaki TAMAKAWA

IPC: H01L23/373 ,  H05K1/18 ,  H01L23/31 ,  H05K1/02 ,  H01L25/065 ,  H01L23/367

CPC classification number: H05K1/181 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/3733 ,  H01L23/4334 ,  H01L23/49816 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15331 ,  H01L2924/1815 ,  H05K1/0204 ,  H05K1/0206 ,  H05K1/0209 ,  H05K1/141 ,  H05K2201/0275 ,  H05K2201/066 ,  H05K2201/10515 ,  H05K2203/1311 ,  H05K2203/1322 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A stacked semiconductor package includes a first semiconductor package including a first circuit board and a first semiconductor device mounted on the first circuit board; a second semiconductor package including a second circuit board and a second semiconductor device mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package; and a heat transfer member provided on the first semiconductor device and a part of the first circuit board, the part being around the first semiconductor device.

Abstract translation: 叠层半导体封装包括：第一半导体封装，包括第一电路板和安装在第一电路板上的第一半导体器件; 第二半导体封装，包括第二电路板和安装在第二电路板上的第二半导体器件，第二半导体封装堆叠在第一半导体封装上; 以及设置在第一半导体器件上的传热部件和第一电路板的一部分，该部分围绕第一半导体器件。

公开(公告)号：US20160027695A1

公开(公告)日：2016-01-28

申请号：US14801437

申请日：2015-07-16

Applicant: J-DEVICES CORPORATION

Inventor： Yoshihiko IKEMOTO ,  Hiroshi INOUE ,  Kiminori ISHIDO ,  Hiroaki MATSUBARA ,  Yukari IMAIZUMI

IPC: H01L21/78 ,  H01L23/48

CPC classification number: H01L21/78 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/19 ,  H01L25/0657 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06565 ,  H01L2225/06586 ,  H01L2224/83

Abstract: The invention provides a semiconductor device low in height and having low heat resistance, and a method of manufacturing the semiconductor device. Disclosed is a semiconductor device including: a support plate 1; a semiconductor chip 2 mounted on one principal surface of the support plate 1 via an adhesive layer, with the element circuit surface of the chip being directed upward; an insulation material layer 4 that seals the semiconductor chip 2 and the periphery of the semiconductor chip; openings formed on an electrode arranged on the element circuit surface of the semiconductor chip 2 in the insulation material layer 4; conductive portions 6 formed in the openings so as to be connected to the electrode of the semiconductor chip; a wiring layer 5 formed on the insulation material layer 4 so as to be connected to the conductive portions 6 and partially extending to the peripheral region of the semiconductor chip 2; and external electrodes 7 formed on the wiring layer 5, wherein the support plate 1 is a flat plate that constitutes the outermost layer of a combined support plate and is separated from the combined support plate in which a plurality of flat plates used in the process of manufacturing the semiconductor device is laminated to each other.

Abstract translation: 本发明提供了一种半导体器件的高度低，耐热性低的半导体器件，以及半导体器件的制造方法。 公开了一种半导体器件，包括：支撑板1; 半导体芯片2，其经由粘合剂层安装在支撑板1的一个主表面上，芯片的元件电路表面朝向上方; 绝缘材料层4，其密封半导体芯片2和半导体芯片的周围; 形成在绝缘材料层4上的布置在半导体芯片2的元件电路表面上的电极上的开口; 形成在开口中以与半导体芯片的电极连接的导电部分6; 形成在绝缘材料层4上的布线层5，以连接到导电部分6并且部分地延伸到半导体芯片2的周边区域; 以及形成在布线层5上的外部电极7，其中支撑板1是构成组合的支撑板的最外层的平板，并且与组合的支撑板分离，在该组合的支撑板中使用多个平板 制造半导体器件彼此层叠。