公开(公告)号：US20220223716A1

公开(公告)日：2022-07-14

申请号：US17705416

申请日：2022-03-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： An-Chi Liu ,  Chun-Hsien Lin

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/201 ,  H01L29/40 ,  H01L29/778

Abstract: A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, a barrier layer on the buffer layer, a gate electrode on the barrier layer, a field plate adjacent to two sides of the gate electrode, and a first passivation layer adjacent to two sides of the gate electrode. Preferably, a sidewall of the field plate includes a first curve.

公开(公告)号：US10991875B2

公开(公告)日：2021-04-27

申请号：US16455674

申请日：2019-06-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： An-Chi Liu ,  Chun-Hsien Lin

IPC: H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22 ,  G11C11/16

Abstract: A semiconductor device includes: a substrate having a magnetic tunneling junction (MTJ) region and a logic region; an inter-metal dielectric (IMD) layer on the substrate; a first metal interconnection in the IMD layer on the logic region; and protrusions adjacent to two sides of the first metal interconnection. Preferably, the first metal interconnection further includes a via conductor and a trench conductor and the protrusions includes a first protrusion on one side of the via conductor and a second protrusion on another side of the via conductor.

公开(公告)号：US20200020792A1

公开(公告)日：2020-01-16

申请号：US16581750

申请日：2019-09-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： An-Chi Liu ,  Chun-Hsien Lin

IPC: H01L29/78 ,  H01L29/20 ,  H01L29/66 ,  H01L21/768 ,  H01L23/535 ,  H01L29/49

Abstract: A method for fabricating a tunnel field effect transistor (TFET) includes the steps of providing a substrate and then forming an interfacial layer on the substrate. Preferably, the step of forming the interfacial layer includes the steps of: performing a plasma treatment process to inject a first gas containing nitrogen; injecting a second gas containing oxygen; and injecting a precursor to react with the first gas and the second gas for forming the interfacial layer.

公开(公告)号：US10276443B2

公开(公告)日：2019-04-30

申请号：US15445928

申请日：2017-02-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Chi Chen ,  Chih-Chung Chen ,  An-Chi Liu ,  Chih-Yueh Li ,  Pei-Ching Yeh ,  Tsung-Chieh Yang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/306 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78

Abstract: A method of removing a fin structure includes providing a substrate. A fin structure extends from the substrate. A mask layer is disposed on a top surface of the fin structure. An organic dielectric layer covers the substrate, the fin structure and the mask layer. A first etching process is performed to entirely remove the mask layer by taking the organic dielectric layer as a mask. Then a second etching process is performed to remove the fin structure. The first etching process is preferably an anisotropic etching process, and the second etching process is an isotropic etching process.

公开(公告)号：US20190080968A1

公开(公告)日：2019-03-14

申请号：US15700175

申请日：2017-09-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Yi Wang ,  Tien-Shan Hsu ,  Yu-Chih Su ,  Chi-Hsuan Cheng ,  Cheng-Pu Chiu ,  Te-Chang Hsu ,  Chin-Yang Hsieh ,  An-Chi Liu ,  Kuan-Lin Chen ,  Yao-Jhan Wang

IPC: H01L21/8234 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/762

Abstract: A method of fabricating fins includes providing a silicon substrate. The silicon substrate is etched to form numerous fin elements. A surface of each of the fin elements is silicon. Etch residues are formed on the fin elements after the silicon substrate is etched. After that, a flush step is performed on the fin elements by flushing the surface of each of the fin elements with fluorocarbons. The etch residues on the fin elements are removed by the flush step. After the flush step, a strip step is performed on the fin elements by treating the surface of each of the fin elements with oxygen plasma.

公开(公告)号：US10069009B2

公开(公告)日：2018-09-04

申请号：US15861700

申请日：2018-01-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： An-Chi Liu ,  Chun-Hsien Lin

IPC: H01L21/00 ,  H01L29/78 ,  H01L23/532 ,  H01L23/535 ,  H01L29/267 ,  H01L29/24 ,  H01L29/16 ,  H01L29/161 ,  H01L29/08 ,  H01L21/768 ,  H01L21/283 ,  H01L29/417 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53266 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7845

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first recess adjacent to two sides of the gate structure; forming an epitaxial layer in the first recess; removing part of the epitaxial layer to forma second recess; and forming an interlayer dielectric (ILD) layer on the gate structure and into the second recess.

公开(公告)号：US20160020104A1

公开(公告)日：2016-01-21

申请号：US14334680

申请日：2014-07-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Lin ,  An-Chi Liu ,  Hsiao-Pang Chou

IPC: H01L21/28 ,  H01L29/49 ,  H01L21/306

CPC classification number: H01L21/28088 ,  H01L21/3212 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7843

Abstract: A metal gate process for polishing and oxidizing includes the following steps. A first dielectric layer having a trench is formed on a substrate. A barrier layer and a metal layer are formed sequentially to cover the trench and the first dielectric layer. A first chemical mechanical polishing process including a slurry of H2O2 with the concentration of 0˜0.5 weight percent (wt. %) is performed to polish the metal layer until the barrier layer on the first dielectric layer is exposed. A second chemical mechanical polishing process including a slurry of H2O2 with the concentration higher than 1 weight percent (wt. %) is performed to polish the barrier layer as well as oxidize a surface of the metal layer remaining in the trench until the first dielectric layer is exposed, thereby a metal oxide layer being formed on the metal layer.

Abstract translation: 用于抛光和氧化的金属浇口工艺包括以下步骤。 在衬底上形成具有沟槽的第一电介质层。 依次形成阻挡层和金属层以覆盖沟槽和第一介电层。 执行包括浓度为0〜0.5重量％（重量％）的H 2 O 2的浆料的第一化学机械抛光工艺，以抛光金属层直到暴露第一​​介电层上的阻挡层。 执行包括浓度高于1重量％（重量％）的H 2 O 2的浆料的第二化学机械抛光方法以抛光阻挡层以及氧化残留在沟槽中的金属层的表面，直到第一介电层 被暴露，从而在金属层上形成金属氧化物层。

公开(公告)号：US20240371968A1

公开(公告)日：2024-11-07

申请号：US18774895

申请日：2024-07-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： An-Chi Liu ,  Chun-Hsien Lin

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/201 ,  H01L29/40 ,  H01L29/778

Abstract: A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, a barrier layer on the buffer layer, a gate electrode on the barrier layer, a field plate adjacent to two sides of the gate electrode, and a first passivation layer adjacent to two sides of the gate electrode. Preferably, a sidewall of the field plate includes a first curve.

公开(公告)号：US12080778B2

公开(公告)日：2024-09-03

申请号：US18238534

申请日：2023-08-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： An-Chi Liu ,  Chun-Hsien Lin

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/201 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/404 ,  H01L29/778

Abstract: A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, a barrier layer on the buffer layer, a gate electrode on the barrier layer, a field plate adjacent to two sides of the gate electrode, and a first passivation layer adjacent to two sides of the gate electrode. Preferably, a sidewall of the field plate includes a first curve.

公开(公告)号：US11758824B2

公开(公告)日：2023-09-12

申请号：US17209251

申请日：2021-03-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： An-Chi Liu ,  Chun-Hsien Lin

IPC: H10N50/80 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

CPC classification number: H10N50/80 ,  G11C11/161 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, an inter-metal dielectric (IMD) layer on the substrate, a MTJ in the IMD layer on the MTJ region, a first metal interconnection in the IMD layer on the logic region, and protrusions adjacent to two sides of the first metal interconnection. Preferably, the MTJ further includes a bottom electrode, a fixed layer, a barrier layer, a free layer, and a top electrode.