公开(公告)号：US20230210028A1

公开(公告)日：2023-06-29

申请号：US18170947

申请日：2023-02-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-Yen PENG ,  Hui-Hsien WEI ,  Wei-Chih WEN ,  Pin-Ren DAI ,  Chien-Min LEE ,  Han-Ting TSAI ,  Jyu-Horng SHIEH ,  Chung-Te LIN

IPC: H10N70/00 ,  H10B61/00 ,  H10B63/00 ,  H10N50/01 ,  H10N50/80 ,  H10N70/20

CPC classification number: H10N70/884 ,  H10B61/22 ,  H10B63/30 ,  H10B63/82 ,  H10B63/84 ,  H10N50/01 ,  H10N50/80 ,  H10N70/023 ,  H10N70/24 ,  H10N70/063 ,  H10N70/245 ,  H10N70/826 ,  H10N70/8416 ,  H10N70/8833

Abstract: An IC structure comprises a substrate, a first dielectric structure, a second dielectric structure, a first via structure, and a memory cell structure. The substrate comprises a memory region and a logic region. The first dielectric structure is over the memory region. The second dielectric structure laterally extends from the first dielectric structure to over the logic region. The second dielectric structure has a thickness less than a thickness of the first dielectric structure. The first via structure extends through the first dielectric structure. A top segment of the first via structure is higher than a top surface of the first dielectric structure. The first memory cell structure is over the first via structure.

公开(公告)号：US20210343937A1

公开(公告)日：2021-11-04

申请号：US17369671

申请日：2021-07-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-Yen PENG ,  Hui-Hsien WEI ,  Wei-Chih WEN ,  Pin-Ren DAI ,  Chien-Min LEE ,  Han-Ting TSAI ,  Jyu-Horng SHIEH ,  Chung-Te LIN

IPC: H01L45/00 ,  H01L27/24 ,  H01L43/02 ,  H01L43/12 ,  H01L27/22

Abstract: An IC structure comprises a substrate, a first material layer, a second material layer, a first via structure, and a memory cell structure. The substrate comprises a memory region and a logic region. The first material layer is disposed on the memory region and the logic region. The second material layer is disposed on the first material layer only at the memory region. The first via structure formed in the first material layer and the second material layer. The memory cell structure is over the first via structure.

公开(公告)号：US20210280579A1

公开(公告)日：2021-09-09

申请号：US17327123

申请日：2021-05-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Te LIN ,  Wei-Yuan LU ,  Feng-Cheng YANG

IPC: H01L27/088 ,  H01L23/522 ,  H01L23/48 ,  H01L29/06 ,  H01L27/06 ,  H01L29/66 ,  H01L27/11 ,  H01L49/02 ,  H01L21/8234 ,  H01L27/22

Abstract: A method comprises growing an epitaxial layer on a first region of a first wafer while remaining a second region of the first wafer exposed; forming a first dielectric layer over the epitaxial layer and the second region; forming a first transistor on a second wafer; forming a second dielectric layer over the first transistor; bonding the first and second dielectric layers; and forming second and third transistors on the epitaxial layer and on the second region of the first wafer, respectively.

公开(公告)号：US20200266339A1

公开(公告)日：2020-08-20

申请号：US16866106

申请日：2020-05-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-Yen PENG ,  Hui-Hsien WEI ,  Wei-Chih WEN ,  Pin-Ren DAI ,  Chien-Min LEE ,  Sheng-Chih LAI ,  Han-Ting TSAI ,  Chung-Te LIN

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  G11C11/16 ,  H01L27/22

Abstract: A memory device includes a bottom electrode, a resistance switching element, a capping layer, a top electrode, a first spacer, and a second spacer. The resistance switching element is over the bottom electrode. The capping layer is over the resistance switching element. The top electrode is over the capping layer. The first spacer extends along a sidewall of the resistance switching element. The second spacer extends along a sidewall of the first spacer and beyond a top of the first spacer, in which the second spacer is in contact with the capping layer.

公开(公告)号：US20200219973A1

公开(公告)日：2020-07-09

申请号：US16826913

申请日：2020-03-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Mark VAN DAL ,  Gerben DOORNBOS ,  Chung-Te LIN

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L27/06 ,  H01L21/8238 ,  H01L21/822 ,  H01L29/40 ,  H01L29/08 ,  H01L27/092 ,  H01L29/786 ,  B82Y10/00 ,  H01L29/775 ,  H01L21/02

Abstract: Semiconductor structures and methods for forming the same are provided. The method includes forming a fin structure over a substrate, and the fin structure includes alternately stacked semiconductor material layers and sacrificial layers. The method further includes forming a dummy gate structure, recessing the fin structure to form an opening, forming first source/drain spacers on sidewalls of the sacrificial layers by performing a first atomic layer deposition (ALD) process, and forming source/drain structure in the opening. The method further includes removing the dummy gate structure and the sacrificial layers to expose the semiconductor material layers and forming a gate structure wrapping around the semiconductor material layers.

公开(公告)号：US20170323877A1

公开(公告)日：2017-11-09

申请号：US15145354

申请日：2016-05-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Te LIN ,  Ting-Wei CHIANG ,  Hui-Zhong ZHUANG ,  Pin-Dai SUE ,  Li-Chun TIEN

IPC: H01L27/02 ,  G06F17/50 ,  H01L27/092 ,  H01L29/423

CPC classification number: H01L27/0207 ,  G06F17/5072 ,  H01L27/092 ,  H01L29/42376 ,  H01L2027/11875

Abstract: A layout includes a plurality of cells and at least one dummy gate electrode continuously extends across the cells. Since the dummy gate electrode is electrically conductive, the dummy gate electrode can be utilized for interconnecting the cells. That is, some signals may travel through the dummy gate electrode rather than through a metal one line or a metal two line. Therefore, an amount of metal one lines and/or metal two lines for interconnecting the cells can be reduced.

公开(公告)号：US20230387108A1

公开(公告)日：2023-11-30

申请号：US18362030

申请日：2023-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Te LIN ,  Wei-Yuan LU ,  Feng-Cheng YANG

IPC: H01L27/088 ,  H01L23/522 ,  H01L23/48 ,  H01L29/06 ,  H01L27/06 ,  H01L29/66 ,  H01L21/8234 ,  H10B10/00 ,  H10B61/00 ,  H10N59/00

CPC classification number: H01L27/088 ,  H01L23/5226 ,  H01L23/481 ,  H01L29/0653 ,  H01L27/0688 ,  H01L29/66545 ,  H01L28/40 ,  H01L21/823475 ,  H01L23/5222 ,  H10B10/12 ,  H10B61/00 ,  H10N59/00 ,  H01L21/8258

Abstract: A method comprises growing an epitaxial layer on a first region of a first wafer while remaining a second region of the first wafer exposed; forming a first dielectric layer over the epitaxial layer and the second region; forming a first transistor on a second wafer; forming a second dielectric layer over the first transistor; bonding the first and second dielectric layers; and forming second and third transistors on the epitaxial layer and on the second region of the first wafer, respectively.

公开(公告)号：US20230253396A1

公开(公告)日：2023-08-10

申请号：US18300142

申请日：2023-04-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fong-yuan CHANG ,  Chun-Chen CHEN ,  Sheng-Hsiung CHEN ,  Ting-Wei CHIANG ,  Chung-Te LIN ,  Jung-Chan YANG ,  Lee-Chung LU ,  Po-Hsiang HUANG

IPC: H01L27/02 ,  H01L27/118 ,  G06F30/394 ,  G06F30/392

CPC classification number: H01L27/0207 ,  G06F30/392 ,  G06F30/394 ,  H01L27/11807 ,  H01L2027/11875

Abstract: The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a keep out area between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the keep out area separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.

公开(公告)号：US20210056175A1

公开(公告)日：2021-02-25

申请号：US16548253

申请日：2019-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Katherine H. CHIANG ,  Chung-Te LIN

IPC: G06F17/50

Abstract: A synergistic design method for an integrated circuit (IC) is provided. The synergistic design method includes forming a standard cell library and a non-standard cell library, implementing an IC design process from a high-level behavior specification through a gate-level netlist to a physical layout, and verifying the physical layout to fabricate the IC. Each standard cell of the standard cell library performs a Boolean logic operation. Each non-standard cell of the non-standard cell library performs a complex function beyond the Boolean logic operation. A conversion process is executed for translating a circuit function into a Boolean network to generate the gate-level netlist based on the standard cells of the standard cell library corresponding to the circuit function. A direct mapping is executed on the non-standard cell by skipping the conversion process during the IC design process to generate the gate-level netlist.

公开(公告)号：US20190252610A1

公开(公告)日：2019-08-15

申请号：US16397871

申请日：2019-04-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tai-Yen PENG ,  Hui-Hsien WEI ,  Wei-Chih WEN ,  Pin-Ren DAI ,  Chien-Min LEE ,  Han-Ting TSAI ,  Jyu-Horng SHIEH ,  Chung-Te LIN

IPC: H01L45/00 ,  H01L43/02 ,  H01L27/24

CPC classification number: H01L45/148 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/2472 ,  H01L27/2481 ,  H01L43/02 ,  H01L43/12 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1675

Abstract: A memory device includes an inter-layer dielectric (ILD) layer, a metallization pattern, an etch stop layer, a metal-containing compound layer, a memory cell, and a bottom electrode via. The metallization pattern is in the ILD layer. The etch stop layer is over the ILD layer. The metal-containing compound layer is over the etch stop layer. The memory cell is over the metal-containing compound layer and includes a bottom electrode, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element. The bottom electrode via connects the bottom electrode to the metallization pattern through the metal-containing compound layer and the etch stop layer.