公开(公告)号：US20240363551A1

公开(公告)日：2024-10-31

申请号：US18764945

申请日：2024-07-05

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yu-Chen LEE ,  Shu-Shen YEH ,  Chia-Kuei HSU ,  Po-Yao LIN ,  Shin-Puu JENG

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L23/562 ,  H01L23/49833 ,  H01L24/32 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/32245

摘要： A semiconductor die package and a method of forming the same are provided. The semiconductor die package includes a package substrate and a semiconductor device disposed over the package substrate. A ring structure is disposed over the package substrate and laterally surrounds the semiconductor device. The ring structure includes a lower ring portion arranged around the periphery of the package substrate. Multiple notches are formed along the outer periphery of the lower ring portion. The ring structure also includes an upper ring portion formed on the lower ring portion. The upper ring portion laterally extends toward the semiconductor device, so that the inner periphery of the upper ring portion is closer to the semiconductor device than the inner periphery of the lower ring portion. An adhesive layer is interposed between the lower ring portion and the package substrate.

公开(公告)号：US20240363474A1

公开(公告)日：2024-10-31

申请号：US18765021

申请日：2024-07-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Sheng LIN ,  Po-Yao LIN ,  Shu-Shen YEH ,  Chin-Hua WANG ,  Shin-Puu JENG

IPC分类号： H01L23/367 ,  H01L21/48 ,  H01L23/31 ,  H01L23/373

CPC分类号： H01L23/3677 ,  H01L21/4882 ,  H01L23/31 ,  H01L23/373

摘要： A method for forming a semiconductor die package is provided. The method includes bonding a first semiconductor die and a second semiconductor die to a package substrate; disposing a lid structure over the package substrate and over the first and second semiconductor dies, wherein the lid structure has a first opening exposing the second semiconductor die; attaching the lid structure to the first semiconductor die using a first thermal interface material (TIM) layer; disposing a heat sink over the lid structure, wherein the heat sink has a first portion located over the lid structure, and a second portion extending into the first opening of the lid structure; and attaching the second portion of the heat sink to the second semiconductor die using a second TIM layer, wherein the first TIM layer has a thermal conductivity higher than a thermal conductivity of the second TIM layer.

公开(公告)号：US20240347407A1

公开(公告)日：2024-10-17

申请号：US18753139

申请日：2024-06-25

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Po-Chen LAI ,  Ming-Chih YEW ,  Po-Yao LIN ,  Chin-Hua WANG ,  Shin-Puu JENG

IPC分类号： H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/14 ,  H01L23/29 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L23/3185 ,  H01L21/565 ,  H01L23/145 ,  H01L23/293 ,  H01L23/3192 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0655 ,  H01L2224/32056 ,  H01L2224/32059 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1811 ,  H01L2924/1815 ,  H01L2924/182 ,  H01L2924/186 ,  H01L2924/35121

摘要： Structures and formation methods of a chip package structure are provided. The method includes mounting semiconductor dies over die regions of an interposer substrate. The adjacent die regions are separated from one another by a gap region of the interposer substrate. The method also includes forming first underfill material layers and a second gap-filling layer over the interposer substrate corresponding to the gap region. The method further includes forming an encapsulating layer over the interposer substrate to surround the semiconductor dies, the first underfill material layers, and the second underfill material layer. The gap region has ends and the first underfill material layers is formed adjacent to the ends of the gap region. The Young's modulus of the second underfill material layer is less than that of the first underfill material layers.

公开(公告)号：US20240332214A1

公开(公告)日：2024-10-03

申请号：US18738188

申请日：2024-06-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Chen LAI ,  Ming-Chih YEW ,  Po-Yao LIN ,  Yu-Sheng LIN ,  Shin-Puu JENG

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065

CPC分类号： H01L23/562 ,  H01L21/563 ,  H01L23/3185 ,  H01L24/73 ,  H01L25/0655 ,  H01L2224/73204

摘要： A package structure and a formation method of a package structure are provided. The package structure includes a circuit substrate and a die package bonded to the circuit substrate through bonding structures. The package structure also includes a reinforcing structure over the circuit substrate. The reinforcing structure partially surrounds a corner of the die package. The package structure further includes an underfill structure surrounding the bonding structure. The underfill structure wraps around an end of the reinforcing structure. In a top view of the package structure, the reinforcing structure has an outer corner, and the underfill structure is spaced apart from the outer corner of the reinforcing structure.

公开(公告)号：US20240332197A1

公开(公告)日：2024-10-03

申请号：US18740881

申请日：2024-06-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chia-Kuei HSU ,  Ming-Chih YEW ,  Shu-Shen YEH ,  Po-Yao LIN ,  Shin-Puu JENG

IPC分类号： H01L23/538 ,  H01L21/768

CPC分类号： H01L23/5384 ,  H01L21/76801 ,  H01L23/5385 ,  H01L23/5386

摘要： A semiconductor package structure includes a first bottom electrical connector and first bottom via structures over the first bottom electrical connector. The semiconductor package structure also includes a trace of a first redistribution layer structure over the first bottom via structures and first via structures over the trace of the first redistribution layer structure. The semiconductor package structure also includes a trace of a second redistribution layer structure over the first via structures and second via structures over the trace of the second redistribution layer structure. The semiconductor package structure also includes a trace of a third redistribution layer structure over the second via structures and partially vertically overlapping the trace of the first redistribution layer structure. The trace of the first redistribution layer structure, the trace of the second redistribution layer structure, and the trace of the third redistribution layer structure extend in different directions.

公开(公告)号：US20240258193A1

公开(公告)日：2024-08-01

申请号：US18631181

申请日：2024-04-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Chen LAI ,  Ming-Chih YEW ,  Po-Yao LIN ,  Chin-Hua WANG ,  Shin-Puu JENG

IPC分类号： H01L23/367 ,  H01L21/48 ,  H01L23/00 ,  H01L23/42 ,  H01L23/433 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L23/3675 ,  H01L21/4817 ,  H01L23/49833 ,  H01L25/0655 ,  H01L23/42 ,  H01L23/433 ,  H01L23/49816 ,  H01L24/73 ,  H01L2924/1611 ,  H01L2924/16152 ,  H01L2924/16251 ,  H01L2924/3511 ,  H01L2924/35121

摘要： A method of forming a semiconductor package structure is provided. The method includes disposing a first semiconductor device on an interposer substrate, disposing the interposer substrate on a carrier substrate, applying a thermal interface material on the first semiconductor device, and attaching a lid on the carrier substrate to cover the first semiconductor device. The interposer substrate is disposed between the carrier substrate and the first semiconductor device. The lid includes a lower surface having a first recess facing the first semiconductor device, and a portion of the thermal interface material is accommodated in the first recess.

公开(公告)号：US20240153840A1

公开(公告)日：2024-05-09

申请号：US18415801

申请日：2024-01-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shin-Puu JENG ,  Po-Yao LIN ,  Feng-Cheng HSU ,  Shuo-Mao CHEN ,  Chin-Hua WANG

IPC分类号： H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L25/18

CPC分类号： H01L23/3675 ,  H01L21/4871 ,  H01L21/56 ,  H01L25/18 ,  H01L25/50

摘要： A method for forming a package structure is provided. The method includes disposing a semiconductor die over a carrier substrate, wherein a removable film is formed over the semiconductor die, disposing a first stacked die package structure over the carrier substrate, wherein a top surface of the removable film is higher than a top surface of the first stacked die package structure, and removing the removable film to expose a top surface of the semiconductor die, wherein a top surface of the semiconductor die is lower than the top surface of the first stacked die package structure.

公开(公告)号：US20240096778A1

公开(公告)日：2024-03-21

申请号：US18513866

申请日：2023-11-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ya-Huei LEE ,  Shu-Shen YEH ,  Kuo-Ching HSU ,  Shyue-Ter LEU ,  Po-Yao LIN ,  Shin-Puu JENG

IPC分类号： H01L23/498

CPC分类号： H01L23/49838 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/1016 ,  H01L2924/20645

摘要： A semiconductor die package is provided. The semiconductor die package includes a semiconductor die and a package substrate supporting and electrically connected to the semiconductor die. The semiconductor die has a corner. The package substrate includes several conductive lines, and one of the conductive lines under the corner of the semiconductor die includes a first line segment and a second line segment connected to the first line segment. The first line segment is linear and extends in a first direction. The second line segment is non-linear and has a varying extension direction.

公开(公告)号：US20230343725A1

公开(公告)日：2023-10-26

申请号：US18344039

申请日：2023-06-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Chen LAI ,  Chin-Hua WANG ,  Ming-Chih YEW ,  Chia-Kuei HSU ,  Li-Ling LIAO ,  Po-Yao LIN ,  Shin-Puu JENG

IPC分类号： H01L23/00 ,  H01L23/538 ,  H01L21/48 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L23/562 ,  H01L23/5383 ,  H01L21/4853 ,  H01L23/5386 ,  H01L25/50 ,  H01L25/0655 ,  H01L2224/73204 ,  H01L24/16 ,  H01L2224/16238 ,  H01L24/73

摘要： A chip package structure is provided. The chip package structure includes a redistribution structure including a dielectric structure and a plurality of wiring layers in or over the dielectric structure. The chip package structure includes a shield bump structure over the redistribution structure and electrically insulated from the wiring layers. The chip package structure includes a first chip structure bonded to the redistribution structure. The first chip structure is electrically insulated from the shield bump structure, and the first chip structure partially overlaps the shield bump structure. The chip package structure includes a second chip structure bonded to the redistribution structure.

公开(公告)号：US20230016849A1

公开(公告)日：2023-01-19

申请号：US17377620

申请日：2021-07-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ya-Huei LEE ,  Shu-Shen YEH ,  Kuo-Ching HSU ,  Shyue-Ter LEU ,  Po-Yao LIN ,  Shin-Puu JENG

IPC分类号： H01L23/498

摘要： A semiconductor die package is provided. The semiconductor die package includes a semiconductor die and a package substrate disposed below the semiconductor die. The semiconductor die has a corner. The package substrate includes several conductive lines, and one of the conductive lines under the corner of the semiconductor die includes a first line segment and a second line segment. The first and second line segments are connected together, and the second line segment has a smaller line width than the first line segment. The first line segment is linear and extends in a first direction. The second line segment is non-linear and has a varying extension direction.