公开(公告)号：US20230017688A1

公开(公告)日：2023-01-19

申请号：US17377583

申请日：2021-07-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Chen LAI ,  Chin-Hua WANG ,  Ming-Chih YEW ,  Chia-Kuei HSU ,  Li-Ling LIAO ,  Po-Yao LIN ,  Shin-Puu JENG

IPC分类号： H01L23/00 ,  H01L23/538 ,  H01L21/48 ,  H01L25/065 ,  H01L25/00

摘要： A method for forming a chip package structure is provided. The method includes forming a dielectric layer over a redistribution structure. The redistribution structure includes a dielectric structure and a plurality of wiring layers in or over the dielectric structure. The method includes forming a first conductive bump structure and a shield bump structure over the dielectric layer. The first conductive bump structure is electrically connected to the wiring layers, and the shield bump structure is electrically insulated from the wiring layers. The method includes bonding a first chip structure to the redistribution structure through the first conductive bump structure. The first chip structure is electrically insulated from the shield bump structure, and the first chip structure extends across a first sidewall of the shield bump structure.

公开(公告)号：US20220336359A1

公开(公告)日：2022-10-20

申请号：US17231310

申请日：2021-04-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chia-Kuei HSU ,  Ming-Chih YEW ,  Shu-Shen YEH ,  Po-Yao LIN ,  Shin-Puu JENG

IPC分类号： H01L23/538 ,  H01L21/768

摘要： A semiconductor package structure includes a first bottom electrical connector, an interposer over the first bottom electrical connector, and a first top electrical connector over the first top via structures. The interposer includes first bottom via structures in contact with the first bottom electrical connector. The interposer also includes a first trace of a first redistribution layer structure over the first bottom via structures. The interposer also includes first via structures over the first redistribution layer. The interposer also includes a first trace of a second redistribution layer structure over the first via structures. The interposer also includes second via structures over the second redistribution layer structure. The first bottom via structures, the first via structures, and the second via structures are separated from each other in a top view.

公开(公告)号：US20240334608A1

公开(公告)日：2024-10-03

申请号：US18740889

申请日：2024-06-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Kuei HSU ,  Ming-Chih YEW ,  Po-Chen LAI ,  Po-Yao LIN ,  Shin-Puu JENG

IPC分类号： H05K1/18 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H05K3/28 ,  H05K3/34

CPC分类号： H05K1/181 ,  H01L25/0655 ,  H05K3/284 ,  H01L23/3185 ,  H01L23/49811 ,  H01L23/5383 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/95001 ,  H05K3/3436 ,  H05K2201/10378 ,  H05K2201/10727 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2203/107

摘要： A method for forming a semiconductor package is provided. The method includes mounting a semiconductor device on a surface of a package substrate. The method also includes forming an underfill element between the semiconductor device and the surface of the package substrate. The underfill element includes a fillet portion that extends laterally beyond the periphery of the semiconductor device and is formed along the periphery of the semiconductor device. The method also includes forming one or more grooves in the fillet portion.

公开(公告)号：US20240096822A1

公开(公告)日：2024-03-21

申请号：US18520971

申请日：2023-11-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Kuei HSU ,  Ming-Chih YEW ,  Shu-Shen YEH ,  Che-Chia YANG ,  Po-Yao LIN ,  Shin-Puu JENG

IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065

CPC分类号： H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0655 ,  H01L2221/68372 ,  H01L2224/16227 ,  H01L2924/18161 ,  H01L2924/3512

摘要： A package structure is provided. The package structure includes a first conductive pad in a first insulating layer, a conductive via in a second insulating layer directly under the first conductive pad, and a first under bump metallurgy structure directly under the first conductive via. In a first horizontal direction, the conductive via is narrower than the first under bump metallurgy structure, and the first under bump metallurgy structure is narrower than the first conductive pad.

公开(公告)号：US20230395520A1

公开(公告)日：2023-12-07

申请号：US17833820

申请日：2022-06-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Li-Ling LIAO ,  Ming-Chih YEW ,  Chia-Kuei HSU ,  Shin-Puu JENG

IPC分类号： H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

CPC分类号： H01L23/5389 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/20 ,  H01L24/19 ,  H01L2924/35121 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L2221/68359 ,  H01L2224/214 ,  H01L21/6835

摘要： A package structure includes an interposer, a die, a conductive terminal and an interconnection structure that is disposed on a first side of the interposer. The die is electrically bonded to the interposer and disposed over the interconnection structure. The conductive terminal is connected to the interposer and the die via a conductive bump. In order to effectively avoid cold joint issues, round or rectangular polyimide structures are first disposed under the bumps to structurally support the bump and sufficiently increase bump height for improved electrical connection and long term reliability of the package structure.

公开(公告)号：US20230299017A1

公开(公告)日：2023-09-21

申请号：US18325205

申请日：2023-05-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shu-Shen YEH ,  Che-Chia YANG ,  Chia-Kuei HSU ,  Ming-Chih YEW ,  Po-Yao LIN ,  Shin-Puu JENG

IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L23/053 ,  H01L23/13

CPC分类号： H01L23/562 ,  H01L21/4878 ,  H01L23/053 ,  H01L23/13

摘要： A semiconductor device package and a method of forming the same are provided. The semiconductor device package includes a substrate, an electronic component, a ring structure, and an adhesive layer. The electronic component is located over a surface of the substrate. The ring structure is located over the surface of the substrate and surrounding the electronic component. The ring structure has a bottom surface facing the surface of the substrate and a top surface opposite the bottom surface. The ring structure includes recesses recessed from and located on the top surface, wherein the recesses are arranged corresponding to the corners of the substrate. The adhesive layer is interposed between the bottom surface of the ring structure and the surface of the substrate.

公开(公告)号：US20230290702A1

公开(公告)日：2023-09-14

申请号：US18318844

申请日：2023-05-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shu-Shen YEH ,  Che-Chia YANG ,  Chia-Kuei HSU ,  Ming-Chih YEW ,  Po-Yao LIN ,  Shin-Puu JENG

IPC分类号： H01L23/373 ,  H01L23/58 ,  H01L23/29

CPC分类号： H01L23/373 ,  H01L23/585 ,  H01L23/29

摘要： A semiconductor die package and a method of forming the same are provided. The semiconductor die package includes a package substrate, semiconductor dies over the package substrate, and an underfill element over the package substrate and surrounding the semiconductor dies. A portion of the underfill element is located between the semiconductor dies. The semiconductor die package also includes lid structures respectively attached to the top surfaces of the semiconductor dies. In plan view, each lid structure is located within the periphery of the top surface of the corresponding semiconductor die. Each lid structure is disconnected from other lid structures, and a gap is formed between adjacent lid structures and located over the portion of the underfill element.

公开(公告)号：US20240363551A1

公开(公告)日：2024-10-31

申请号：US18764945

申请日：2024-07-05

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yu-Chen LEE ,  Shu-Shen YEH ,  Chia-Kuei HSU ,  Po-Yao LIN ,  Shin-Puu JENG

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L23/562 ,  H01L23/49833 ,  H01L24/32 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/32245

摘要： A semiconductor die package and a method of forming the same are provided. The semiconductor die package includes a package substrate and a semiconductor device disposed over the package substrate. A ring structure is disposed over the package substrate and laterally surrounds the semiconductor device. The ring structure includes a lower ring portion arranged around the periphery of the package substrate. Multiple notches are formed along the outer periphery of the lower ring portion. The ring structure also includes an upper ring portion formed on the lower ring portion. The upper ring portion laterally extends toward the semiconductor device, so that the inner periphery of the upper ring portion is closer to the semiconductor device than the inner periphery of the lower ring portion. An adhesive layer is interposed between the lower ring portion and the package substrate.

公开(公告)号：US20240332197A1

公开(公告)日：2024-10-03

申请号：US18740881

申请日：2024-06-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chia-Kuei HSU ,  Ming-Chih YEW ,  Shu-Shen YEH ,  Po-Yao LIN ,  Shin-Puu JENG

IPC分类号： H01L23/538 ,  H01L21/768

CPC分类号： H01L23/5384 ,  H01L21/76801 ,  H01L23/5385 ,  H01L23/5386

摘要： A semiconductor package structure includes a first bottom electrical connector and first bottom via structures over the first bottom electrical connector. The semiconductor package structure also includes a trace of a first redistribution layer structure over the first bottom via structures and first via structures over the trace of the first redistribution layer structure. The semiconductor package structure also includes a trace of a second redistribution layer structure over the first via structures and second via structures over the trace of the second redistribution layer structure. The semiconductor package structure also includes a trace of a third redistribution layer structure over the second via structures and partially vertically overlapping the trace of the first redistribution layer structure. The trace of the first redistribution layer structure, the trace of the second redistribution layer structure, and the trace of the third redistribution layer structure extend in different directions.

公开(公告)号：US20230343725A1

公开(公告)日：2023-10-26

申请号：US18344039

申请日：2023-06-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Chen LAI ,  Chin-Hua WANG ,  Ming-Chih YEW ,  Chia-Kuei HSU ,  Li-Ling LIAO ,  Po-Yao LIN ,  Shin-Puu JENG

IPC分类号： H01L23/00 ,  H01L23/538 ,  H01L21/48 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L23/562 ,  H01L23/5383 ,  H01L21/4853 ,  H01L23/5386 ,  H01L25/50 ,  H01L25/0655 ,  H01L2224/73204 ,  H01L24/16 ,  H01L2224/16238 ,  H01L24/73

摘要： A chip package structure is provided. The chip package structure includes a redistribution structure including a dielectric structure and a plurality of wiring layers in or over the dielectric structure. The chip package structure includes a shield bump structure over the redistribution structure and electrically insulated from the wiring layers. The chip package structure includes a first chip structure bonded to the redistribution structure. The first chip structure is electrically insulated from the shield bump structure, and the first chip structure partially overlaps the shield bump structure. The chip package structure includes a second chip structure bonded to the redistribution structure.