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公开(公告)号：US20240363551A1
公开(公告)日：2024-10-31
申请号：US18764945
申请日：2024-07-05
发明人： Yu-Chen LEE , Shu-Shen YEH , Chia-Kuei HSU , Po-Yao LIN , Shin-Puu JENG
IPC分类号： H01L23/00 , H01L23/498 , H01L25/065
CPC分类号： H01L23/562 , H01L23/49833 , H01L24/32 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L2224/32245
摘要： A semiconductor die package and a method of forming the same are provided. The semiconductor die package includes a package substrate and a semiconductor device disposed over the package substrate. A ring structure is disposed over the package substrate and laterally surrounds the semiconductor device. The ring structure includes a lower ring portion arranged around the periphery of the package substrate. Multiple notches are formed along the outer periphery of the lower ring portion. The ring structure also includes an upper ring portion formed on the lower ring portion. The upper ring portion laterally extends toward the semiconductor device, so that the inner periphery of the upper ring portion is closer to the semiconductor device than the inner periphery of the lower ring portion. An adhesive layer is interposed between the lower ring portion and the package substrate.
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公开(公告)号：US20240363474A1
公开(公告)日：2024-10-31
申请号：US18765021
申请日：2024-07-05
发明人： Yu-Sheng LIN , Po-Yao LIN , Shu-Shen YEH , Chin-Hua WANG , Shin-Puu JENG
IPC分类号： H01L23/367 , H01L21/48 , H01L23/31 , H01L23/373
CPC分类号： H01L23/3677 , H01L21/4882 , H01L23/31 , H01L23/373
摘要： A method for forming a semiconductor die package is provided. The method includes bonding a first semiconductor die and a second semiconductor die to a package substrate; disposing a lid structure over the package substrate and over the first and second semiconductor dies, wherein the lid structure has a first opening exposing the second semiconductor die; attaching the lid structure to the first semiconductor die using a first thermal interface material (TIM) layer; disposing a heat sink over the lid structure, wherein the heat sink has a first portion located over the lid structure, and a second portion extending into the first opening of the lid structure; and attaching the second portion of the heat sink to the second semiconductor die using a second TIM layer, wherein the first TIM layer has a thermal conductivity higher than a thermal conductivity of the second TIM layer.
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公开(公告)号：US20240332197A1
公开(公告)日：2024-10-03
申请号：US18740881
申请日：2024-06-12
发明人： Chia-Kuei HSU , Ming-Chih YEW , Shu-Shen YEH , Po-Yao LIN , Shin-Puu JENG
IPC分类号： H01L23/538 , H01L21/768
CPC分类号： H01L23/5384 , H01L21/76801 , H01L23/5385 , H01L23/5386
摘要： A semiconductor package structure includes a first bottom electrical connector and first bottom via structures over the first bottom electrical connector. The semiconductor package structure also includes a trace of a first redistribution layer structure over the first bottom via structures and first via structures over the trace of the first redistribution layer structure. The semiconductor package structure also includes a trace of a second redistribution layer structure over the first via structures and second via structures over the trace of the second redistribution layer structure. The semiconductor package structure also includes a trace of a third redistribution layer structure over the second via structures and partially vertically overlapping the trace of the first redistribution layer structure. The trace of the first redistribution layer structure, the trace of the second redistribution layer structure, and the trace of the third redistribution layer structure extend in different directions.
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公开(公告)号：US20240096778A1
公开(公告)日：2024-03-21
申请号：US18513866
申请日：2023-11-20
发明人： Ya-Huei LEE , Shu-Shen YEH , Kuo-Ching HSU , Shyue-Ter LEU , Po-Yao LIN , Shin-Puu JENG
IPC分类号： H01L23/498
CPC分类号： H01L23/49838 , H01L23/49822 , H01L24/16 , H01L2224/16227 , H01L2924/1016 , H01L2924/20645
摘要： A semiconductor die package is provided. The semiconductor die package includes a semiconductor die and a package substrate supporting and electrically connected to the semiconductor die. The semiconductor die has a corner. The package substrate includes several conductive lines, and one of the conductive lines under the corner of the semiconductor die includes a first line segment and a second line segment connected to the first line segment. The first line segment is linear and extends in a first direction. The second line segment is non-linear and has a varying extension direction.
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公开(公告)号：US20230016849A1
公开(公告)日：2023-01-19
申请号：US17377620
申请日：2021-07-16
发明人： Ya-Huei LEE , Shu-Shen YEH , Kuo-Ching HSU , Shyue-Ter LEU , Po-Yao LIN , Shin-Puu JENG
IPC分类号： H01L23/498
摘要： A semiconductor die package is provided. The semiconductor die package includes a semiconductor die and a package substrate disposed below the semiconductor die. The semiconductor die has a corner. The package substrate includes several conductive lines, and one of the conductive lines under the corner of the semiconductor die includes a first line segment and a second line segment. The first and second line segments are connected together, and the second line segment has a smaller line width than the first line segment. The first line segment is linear and extends in a first direction. The second line segment is non-linear and has a varying extension direction.
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公开(公告)号：US20220384391A1
公开(公告)日：2022-12-01
申请号：US17818432
申请日：2022-08-09
发明人： Shu-Shen YEH , Po-Yao LIN , Shin-Puu JENG , Po-Chen LAI , Kuang-Chun LEE , Che-Chia YANG , Chin-Hua WANG , Yi Hang LIN
IPC分类号： H01L25/065 , H01L23/31 , H01L23/498 , H01L23/00 , H01L25/00
摘要： A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes a first chip structure and a second chip structure over the wiring substrate. The first chip structure is spaced apart from the second chip structure by a gap. The chip package structure includes a ring structure over the wiring substrate. The ring structure has a first opening, the first chip structure and the second chip structure are in the first opening, the first opening has a first inner wall, the first inner wall has a first recess, and the gap extends toward the first recess.
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公开(公告)号：US20220384390A1
公开(公告)日：2022-12-01
申请号：US17817705
申请日：2022-08-05
发明人： Che-Chia YANG , Shu-Shen YEH , Po-Chen LAI , Ming-Chih YEW , Po-Yao LIN , Shin-Puu JENG
IPC分类号： H01L25/065 , H01L23/00 , H01L25/00 , H01L23/31
摘要： A semiconductor device package is provided. The semiconductor device package includes a substrate, a first package component, a second package component, and at least one dummy die. The first and second package components are disposed over and bonded to the substrate. The first and second package components are different types of electronic components that provide different functions. The dummy die is disposed over and attached to the substrate. The dummy die is located between the first and second package components and is electrically isolated from the substrate.
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公开(公告)号：US20220367314A1
公开(公告)日：2022-11-17
申请号：US17318163
申请日：2021-05-12
发明人： Shu-Shen YEH , Che-Chia YANG , Chia-Kuei HSU , Ming-Chih YEW , Po-Yao LIN , Shin-Puu JENG
IPC分类号： H01L23/373 , H01L23/29 , H01L23/58
摘要： A semiconductor die package and a method of forming the same are provided. The semiconductor die package includes a package substrate, an interposer substrate over the package substrate, semiconductor dies over the interposer substrate, and an underfill element over the interposer substrate and between the semiconductor dies and interposer substrate. The semiconductor die package also includes a ring structure and one or more lid structures separated from the ring structure. The ring structure is coupled to the package substrate to control warpage. The lid structures are coupled to the top surfaces of the semiconductor dies to control warpage and help heat dissipation. In addition, the lid structures define a gap to allow a portion of the underfill element between the adjacent semiconductor dies to be exposed, so that stress concentration on that portion can be avoided or reduced. Accordingly, the reliability of the semiconductor die package is improved.
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公开(公告)号：US20240153839A1
公开(公告)日：2024-05-09
申请号：US18411392
申请日：2024-01-12
发明人： Shu-Shen YEH , Po-Yao LIN , Chin-Hua WANG , Yu-Sheng LIN , Shin-Puu JENG
IPC分类号： H01L23/367 , H01L21/48 , H01L23/00 , H01L23/31 , H01L23/498 , H01L25/065
CPC分类号： H01L23/3675 , H01L21/4857 , H01L21/4882 , H01L23/3157 , H01L23/49816 , H01L23/49822 , H01L23/49833 , H01L23/49838 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/73 , H01L25/0655 , H01L2224/16235 , H01L2224/29017 , H01L2224/32225 , H01L2224/73204 , H01L2924/1815 , H01L2924/182 , H01L2924/3511 , H01L2924/35121
摘要： A semiconductor package structure includes an interposer substrate formed over a package substrate. The structure also includes a die disposed over the interposer substrate. The structure also includes a first heat spreader disposed over the package substrate. The structure also includes a second heat spreader disposed over the die and connected to the first heat spreader. The coefficient of thermal expansion (CTE) of the first heat spreader and the coefficient of thermal expansion of the second heat spreader are different.
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公开(公告)号：US20240120294A1
公开(公告)日：2024-04-11
申请号：US18391891
申请日：2023-12-21
发明人： Shu-Shen YEH , Chin-Hua WANG , Kuang-Chun LEE , Po-Yao LIN , Shyue-Ter LEU , Shin-Puu JENG
IPC分类号： H01L23/00 , H01L23/04 , H01L23/10 , H01L23/367
CPC分类号： H01L23/562 , H01L23/04 , H01L23/10 , H01L23/367 , H01L23/3675 , H01L23/49816
摘要： A chip package includes a substrate, a semiconductor chip, and a thermal conductive structure. The chip package includes a first and a second support structures below the thermal conductive structure. The first and the second support structures connect the substrate and corners of the thermal conductive structure. The thermal conductive structure has a side edge connecting the first and the second support structures. The first and the second support structures and the side edge together define of an opening exposing a space surrounding the semiconductor chip. The first and the second support structures are disposed along a side of the substrate. The first support structure is laterally separated from the side of the substrate by a first lateral distance. The side edge of the thermal conductive structure is laterally separated from the side of the substrate by a second lateral distance different than the first lateral distance.
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