公开(公告)号：US20240153840A1

公开(公告)日：2024-05-09

申请号：US18415801

申请日：2024-01-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shin-Puu JENG ,  Po-Yao LIN ,  Feng-Cheng HSU ,  Shuo-Mao CHEN ,  Chin-Hua WANG

IPC分类号： H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L25/18

CPC分类号： H01L23/3675 ,  H01L21/4871 ,  H01L21/56 ,  H01L25/18 ,  H01L25/50

摘要： A method for forming a package structure is provided. The method includes disposing a semiconductor die over a carrier substrate, wherein a removable film is formed over the semiconductor die, disposing a first stacked die package structure over the carrier substrate, wherein a top surface of the removable film is higher than a top surface of the first stacked die package structure, and removing the removable film to expose a top surface of the semiconductor die, wherein a top surface of the semiconductor die is lower than the top surface of the first stacked die package structure.

公开(公告)号：US20220189884A1

公开(公告)日：2022-06-16

申请号：US17688647

申请日：2022-03-07

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Yao CHUANG ,  Po-Hao TSAI ,  Shin-Puu JENG ,  Shuo-Mao CHEN ,  Ming-Chih YEW

IPC分类号： H01L23/552 ,  H01L23/538 ,  H01L23/31 ,  H01L21/48 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H05K1/02 ,  H01L23/498 ,  H01L25/16

摘要： A method for forming a chip package is provided. The method includes forming a plurality of conductive structures over a carrier substrate. The method also includes disposing a semiconductor die over the carrier substrate such that the conductive ti structures surround the semiconductor die. The method further includes disposing a shielding element over the semiconductor die and the conductive structures. The shielding element is electrically connected to the conductive structures.

公开(公告)号：US20230260890A1

公开(公告)日：2023-08-17

申请号：US18307091

申请日：2023-04-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shin-Puu JENG ,  Po-Hao TSAI ,  Po-Yao CHUANG ,  Feng-Cheng HSU ,  Shuo-Mao CHEN ,  Techi WONG

IPC分类号： H01L23/498 ,  H01L25/10 ,  H01L21/52 ,  H01L23/053 ,  H01L21/56 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L25/00

CPC分类号： H01L23/49838 ,  H01L25/105 ,  H01L23/49822 ,  H01L21/52 ,  H01L23/053 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L24/27 ,  H01L21/6835 ,  H01L24/16 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4853 ,  H01L24/96 ,  H01L25/50 ,  H01L24/92 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/81191 ,  H01L21/561 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/81005 ,  H01L2224/16235 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1041 ,  H01L2224/73253 ,  H01L2224/92225 ,  H01L2224/32225 ,  H01L2224/83191 ,  H01L2224/0401 ,  H01L2924/15311 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2224/26175 ,  H01L2224/73204 ,  H01L23/3128

摘要： A chip package is provided. The chip package includes a substrate structure. The substrate structure includes a redistribution structure having a conductive pad. The substrate structure includes a first insulating layer under the redistribution structure. The substrate structure includes a conductive via structure passing through the first insulating layer. The conductive via structure is under and electrically connected with the conductive pad. The substrate structure includes a second insulating layer disposed between the redistribution structure and the first insulating layer. The chip package includes a first chip over the redistribution structure and electrically connected to the conductive via structure through the redistribution structure. The chip package includes a second chip under the substrate structure.

公开(公告)号：US20230223360A1

公开(公告)日：2023-07-13

申请号：US18182728

申请日：2023-03-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shin-Puu JENG ,  Po-Yao LIN ,  Shuo-Mao CHEN ,  Chia-Hsiang LIN

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/64 ,  H01L23/31 ,  H01L23/538 ,  H01L21/683

CPC分类号： H01L23/562 ,  H01L21/565 ,  H01L21/4857 ,  H01L23/642 ,  H01L23/3128 ,  H01L23/5386 ,  H01L21/6835 ,  H01L23/5383 ,  H01L24/16 ,  H01L21/4853 ,  H01L2221/68372 ,  H01L2224/16227 ,  H01L2924/19103 ,  H01L2924/19041 ,  H01L2924/3511

摘要： A package structure is provided. The package structure includes a reinforced plate and multiple conductive structures penetrating through the reinforced plate. The package structure also includes a redistribution structure over the reinforced plate. The redistribution structure has multiple polymer-containing layers and multiple conductive features. The package structure further includes multiple chip structures bonded to the redistribution structure through multiple solder bumps. In addition, the package structure includes a protective layer surrounding the chip structures.

公开(公告)号：US20230378076A1

公开(公告)日：2023-11-23

申请号：US18358714

申请日：2023-07-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shin-Puu JENG ,  Shuo-Mao CHEN ,  Feng-Cheng HSU ,  Po-Yao LIN

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L21/78 ,  H01L23/31 ,  H01L25/16

CPC分类号： H01L23/5385 ,  H01L24/81 ,  H01L21/568 ,  H01L21/4853 ,  H01L21/78 ,  H01L21/561 ,  H01L23/5383 ,  H01L24/16 ,  H01L23/3128 ,  H01L23/562 ,  H01L25/162 ,  H01L21/4857 ,  H01L24/13 ,  H01L2224/16227 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144

摘要： A chip package structure is provided. The chip package structure includes a first redistribution structure having a first surface and a second surface. The first redistribution structure includes a first pad and a second pad, the first pad is adjacent to the first surface, and the second pad is adjacent to and exposed from the second surface. The chip package structure includes a chip package bonded to the first pad through a first bump, wherein a first width of the first pad decreases in a first direction away from the chip package, and a second width of the second pad decreases in the first direction. The chip package structure includes a second bump over the second pad.

公开(公告)号：US20210264094A1

公开(公告)日：2021-08-26

申请号：US17319687

申请日：2021-05-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Feng Wei KUO ,  Shuo-Mao CHEN ,  Chin-Yuan HUANG ,  Kai-Yun LIN ,  Ho-Hsiang CHEN ,  Chewn-Pu JOU

IPC分类号： G06F30/398 ,  H01L23/544 ,  H01L25/07

摘要： A method of verifying an integrated circuit stack includes adding a dummy layer to a contact pad of a functional circuit, wherein a location of the dummy layer is determined based on a location of a contact pad of a connecting substrate. The method further includes converting the dummy layer location to the connecting substrate. The method further includes performing a layout versus schematic (LVS) check of the connecting substrate including the dummy layer in response to a determination that the dummy layer is aligned with the contact pad of the connecting substrate.

公开(公告)号：US20210242122A1

公开(公告)日：2021-08-05

申请号：US17233852

申请日：2021-04-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shin-Puu JENG ,  Po-Hao TSAI ,  Po-Yao CHUANG ,  Feng-Cheng HSU ,  Shuo-Mao CHEN ,  Techi WONG

IPC分类号： H01L23/498 ,  H01L25/10 ,  H01L21/52 ,  H01L23/053 ,  H01L21/56 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L25/00

摘要： A chip package is provided. The chip package includes a substrate structure. The substrate structure includes a redistribution structure, a third insulating layer, and a fourth insulating layer. The first wiring layer has a conductive pad. The conductive pad is exposed from the first insulating layer, and the second wiring layer protrudes from the second insulating layer. The third insulating layer is under the first insulating layer of the redistribution structure and has a through hole corresponding to the conductive pad of the first wiring layer. The conductive pad overlaps the third insulating layer. The fourth insulating layer disposed between the redistribution structure and the third insulating layer. The chip package includes a chip over the redistribution structure and electrically connected to the first wiring layer and the second wiring layer.

公开(公告)号：US20160239598A1

公开(公告)日：2016-08-18

申请号：US14621054

申请日：2015-02-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Feng Wei KUO ,  Shuo-Mao CHEN ,  Chin-Yuan HUANG ,  Kai-Yun LIN ,  Ho-Hsiang CHEN ,  Chewn-Pu JOU

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  H01L25/07

摘要： A method of verifying an integrated circuit stack includes adding a dummy layer to a contact pad of a functional circuit, wherein a location of the dummy layer is determined based on a location of a contact pad of a connecting substrate. The method further includes converting the dummy layer location to the connecting substrate; and determining whether the dummy layer is aligned with the contact pad of the connecting substrate. The method further includes performing an LVS check of the connecting substrate including the dummy layer; and adjusting the dummy layer location in the functional circuit if the dummy layer location is misaligned with the contact pad of the connecting substrate or the connecting substrate fails the LVS check. The method further includes repeating the converting step, the determining step, and the performing the LVS check step based on the adjusted dummy layer location.

摘要翻译： 验证集成电路堆栈的方法包括将虚设层添加到功能电路的接触焊盘，其中基于连接衬底的接触焊盘的位置来确定虚设层的位置。 该方法还包括将虚拟层位置转换为连接衬底; 以及确定所述虚设层是否与所述连接基板的所述接触焊盘对准。 该方法还包括执行包括虚拟层的连接基板的LVS检查; 并且如果虚设层位置与连接基板的接触焊盘不对准或连接基板失效，则调整功能电路中的虚设层位置。 该方法还包括基于调整的虚拟层位置重复转换步骤，确定步骤和执行LVS校验步骤。

公开(公告)号：US20240347439A1

公开(公告)日：2024-10-17

申请号：US18753091

申请日：2024-06-25

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shin-Puu JENG ,  Po-Hao TSAI ,  Po-Yao CHUANG ,  Feng-Cheng HSU ,  Shuo-Mao CHEN ,  Techi WONG

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L21/52 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/053 ,  H01L23/31 ,  H01L25/00 ,  H01L25/10

CPC分类号： H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/52 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/053 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01L21/561 ,  H01L23/3128 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/0401 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/83191 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/15311

摘要： A chip package is provided. The chip package includes a substrate structure including: a redistribution structure having a conductive pad; and an insulating layer under the redistribution structure. The chip package includes a first chip over the redistribution structure. The chip package includes a second chip under the substrate structure. A top portion of the second chip extends into the insulating layer from a bottom surface of the insulating layer, the bottom surface faces away from the first chip, and a portion of the insulating layer is between the second chip and the redistribution structure. The chip package includes a first molding layer over the redistribution structure and the first chip. A first sidewall of the first molding layer and a second sidewall of the redistribution structure are substantially level with each other.

公开(公告)号：US20230369150A1

公开(公告)日：2023-11-16

申请号：US18359923

申请日：2023-07-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shin-Puu JENG ,  Feng-Cheng HSU ,  Shuo-Mao CHEN

IPC分类号： H01L23/13 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/00

CPC分类号： H01L23/13 ,  H01L23/49833 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/16 ,  H01L24/17 ,  H01L25/50 ,  H01L25/18

摘要： A package structure and a method of forming the same are provided. The package structure includes a package substrate, an interposer substrate, and a semiconductor device. The interposer substrate is disposed over the package substrate, wherein the interposer substrate has a bottom surface facing the package substrate and a first cavity formed on the bottom surface. The semiconductor device is disposed in the first cavity. The package substrate has a top surface facing the interposer substrate and a second cavity formed on the top surface, wherein the second cavity is configured to accommodate the semiconductor device.