公开(公告)号：US20240072056A1

公开(公告)日：2024-02-29

申请号：US18334099

申请日：2023-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junggun You ,  Gigwan Park

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823878 ,  H01L27/0922 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/78696 ,  H01L2029/42388

Abstract: A semiconductor device includes first and second active fins on first and second regions of a substrate, an isolation pattern on a boundary between the first and second regions and portions of the first and second regions adjacent thereto and separating the first and second active fins, a first gate structure on the first active fin and the isolation pattern on the first region, a second gate structure on the second active fin and the isolation pattern on the second region, a first source/drain layer on the first active fin adjacent to the first gate structure, and a second source/drain layer on the second active fin adjacent to the second gate structure. A width of a portion of the first gate structure overlapping the first active fin is greater than that of a portion of the second gate structure overlapping the second active fin.

公开(公告)号：US20180331103A1

公开(公告)日：2018-11-15

申请号：US16017024

申请日：2018-06-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonkeun Chung ,  Gigwan Park ,  Huyong Lee ,  TaekSoo Jeon ,  Sangjin Hyun

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L27/0922 ,  H01L21/28114 ,  H01L21/82345 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/435 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a substrate having an active pattern thereon, a gate electrode intersecting the active pattern, and a spacer on a sidewall of the gate electrode. The gate electrode includes a first metal pattern adjacent to the active pattern. The first metal pattern has a first portion parallel to the sidewall and a second portion parallel to the substrate. A top surface of the first portion has a descent in a direction from the spacer towards the second portion.

公开(公告)号：US20170186746A1

公开(公告)日：2017-06-29

申请号：US15372876

申请日：2016-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonkeun Chung ,  Gigwan Park ,  Huyong Lee ,  TaekSoo Jeon ,  Sangjin Hyun

IPC: H01L27/092 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L27/0922 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/435 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/785

Abstract: A semiconductor device includes a substrate having an active pattern thereon, a gate electrode intersecting the active pattern, and a spacer on a sidewall of the gate electrode. The gate electrode includes a first metal pattern adjacent to the active pattern. The first metal pattern has a first portion parallel to the sidewall and a second portion parallel to the substrate. A top surface of the first portion has a descent in a direction from the spacer towards the second portion.

公开(公告)号：USRE49963E1

公开(公告)日：2024-05-07

申请号：US17155615

申请日：2021-01-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Hwan Kim ,  Gigwan Park ,  Junggun You ,  DongSuk Shin ,  Jin-Wook Kim

IPC: H01L29/78 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/535 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66 ,  H10B10/00 ,  H01L27/12 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/535 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/66636 ,  H10B10/12 ,  H10B10/18 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/165

Abstract: A semiconductor device includes first and second active patterns protruding upward from a substrate, a gate electrode crossing the first and second active patterns and extending in a first direction, a first source/drain region on the first active pattern and on at least one side of the gate electrode, and a second source/drain region on the second active pattern and on at least one side of the gate electrode. The first and second source/drain regions have a conductivity type different from each other, and the second source/drain region has a bottom surface in contact with a top surface of the second active pattern and at a lower level than that of a bottom surface of the first source/drain region in contact with a top surface of the first active pattern. The first active pattern has a first width smaller than a second width of the second active pattern.

公开(公告)号：US10784376B2

公开(公告)日：2020-09-22

申请号：US16450193

申请日：2019-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Hwan Kim ,  Gigwan Park ,  Junggun You ,  DongSuk Shin ,  Jin-Wook Kim

IPC: H01L29/78 ,  H01L21/8238 ,  H01L23/535 ,  H01L27/092 ,  H01L27/11 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66 ,  H01L27/12 ,  H01L21/84 ,  H01L29/165

Abstract: A semiconductor device includes first and second active patterns protruding upward from a substrate, a gate electrode crossing the first and second active patterns and extending in a first direction, a first source/drain region on the first active pattern and on at least one side of the gate electrode, and a second source/drain region on the second active pattern and on at least one side of the gate electrode. The first and second source/drain regions have a conductivity type different from each other, and the second source/drain region has a bottom surface in contact with a top surface of the second active pattern and at a lower level than that of a bottom surface of the first source/drain region in contact with a top surface of the first active pattern. The first active pattern has a first width smaller than a second width of the second active pattern.

公开(公告)号：US10468411B2

公开(公告)日：2019-11-05

申请号：US16017024

申请日：2018-06-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonkeun Chung ,  Gigwan Park ,  Huyong Lee ,  TaekSoo Jeon ,  Sangjin Hyun

IPC: H01L29/06 ,  H01L29/423 ,  H01L21/28 ,  H01L27/092 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/49 ,  H01L29/78 ,  H01L29/66 ,  H01L29/43

Abstract: A semiconductor device includes a substrate having an active pattern thereon, a gate electrode intersecting the active pattern, and a spacer on a sidewall of the gate electrode. The gate electrode includes a first metal pattern adjacent to the active pattern. The first metal pattern has a first portion parallel to the sidewall and a second portion parallel to the substrate. A top surface of the first portion has a descent in a direction from the spacer towards the second portion.

公开(公告)号：US20190319127A1

公开(公告)日：2019-10-17

申请号：US16450193

申请日：2019-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Hwan Kim ,  Gigwan Park ,  Junggun You ,  DongSuk Shin ,  Jin-Wook Kim

IPC: H01L29/78 ,  H01L27/11 ,  H01L29/16 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/66 ,  H01L23/535

Abstract: A semiconductor device includes first and second active patterns protruding upward from a substrate, a gate electrode crossing the first and second active patterns and extending in a first direction, a first source/drain region on the first active pattern and on at least one side of the gate electrode, and a second source/drain region on the second active pattern and on at least one side of the gate electrode. The first and second source/drain regions have a conductivity type different from each other, and the second source/drain region has a bottom surface in contact with a top surface of the second active pattern and at a lower level than that of a bottom surface of the first source/drain region in contact with a top surface of the first active pattern. The first active pattern has a first width smaller than a second width of the second active pattern.

公开(公告)号：US10411131B2

公开(公告)日：2019-09-10

申请号：US16111854

申请日：2018-08-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Hwan Kim ,  Gigwan Park ,  Junggun You ,  DongSuk Shin ,  Jin-Wook Kim

IPC: H01L29/78 ,  H01L21/8238 ,  H01L23/535 ,  H01L27/092 ,  H01L27/11 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66

Abstract: A semiconductor device includes first and second active patterns protruding upward from a substrate, a gate electrode crossing the first and second active patterns and extending in a first direction, a first source/drain region on the first active pattern and on at least one side of the gate electrode, and a second source/drain region on the second active pattern and on at least one side of the gate electrode. The first and second source/drain regions have a conductivity type different from each other, and the second source/drain region has a bottom surface in contact with a top surface of the second active pattern and at a lower level than that of a bottom surface of the first source/drain region in contact with a top surface of the first active pattern. The first active pattern has a first width smaller than a second width of the second active pattern.

公开(公告)号：US10205020B2

公开(公告)日：2019-02-12

申请号：US15348586

申请日：2016-11-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongseok Lee ,  Jeongyun Lee ,  Gigwan Park ,  Keo Myoung Shin ,  Hyunji Kim ,  Sangduk Park

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8238 ,  H01L49/02 ,  H01L29/165

Abstract: A semiconductor device includes an active pattern having sidewalls defined by a device isolation pattern disposed on a substrate and an upper portion protruding from a top surface of the device isolation pattern, a liner insulating layer on the sidewalls of the active pattern, a gate structure on the active pattern, and source/drain regions at both sides of the gate structure. The liner insulating layer includes a first liner insulating layer and a second liner insulating layer having a top surface higher than a top surface of the first liner insulating layer. Each of the source/drain regions includes a first portion defined by the second liner insulating layer, and a second portion protruding upward from the second liner insulating layer and covering the top surface of the first liner insulating layer.

公开(公告)号：US10090413B2

公开(公告)日：2018-10-02

申请号：US15288080

申请日：2016-10-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Hwan Kim ,  Gigwan Park ,  Junggun You ,  DongSuk Shin ,  Jin-Wook Kim

IPC: H01L29/78 ,  H01L29/16 ,  H01L23/535 ,  H01L27/11 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66

Abstract: A semiconductor device includes first and second active patterns protruding upward from a substrate, a gate electrode crossing the first and second active patterns and extending in a first direction, a first source/drain region on the first active pattern and on at least one side of the gate electrode, and a second source/drain region on the second active pattern and on at least one side of the gate electrode. The first and second source/drain regions have a conductivity type different from each other, and the second source/drain region has a bottom surface in contact with a top surface of the second active pattern and at a lower level than that of a bottom surface of the first source/drain region in contact with a top surface of the first active pattern. The first active pattern has a first width smaller than a second width of the second active pattern.