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公开(公告)号:US10468411B2
公开(公告)日:2019-11-05
申请号:US16017024
申请日:2018-06-25
Applicant: Samsung Electronics Co., Ltd.
Inventor: Wonkeun Chung , Gigwan Park , Huyong Lee , TaekSoo Jeon , Sangjin Hyun
IPC: H01L29/06 , H01L29/423 , H01L21/28 , H01L27/092 , H01L21/8234 , H01L21/8238 , H01L27/088 , H01L29/49 , H01L29/78 , H01L29/66 , H01L29/43
Abstract: A semiconductor device includes a substrate having an active pattern thereon, a gate electrode intersecting the active pattern, and a spacer on a sidewall of the gate electrode. The gate electrode includes a first metal pattern adjacent to the active pattern. The first metal pattern has a first portion parallel to the sidewall and a second portion parallel to the substrate. A top surface of the first portion has a descent in a direction from the spacer towards the second portion.
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公开(公告)号:US10043803B2
公开(公告)日:2018-08-07
申请号:US15372876
申请日:2016-12-08
Applicant: Samsung Electronics Co., Ltd.
Inventor: Wonkeun Chung , Gigwan Park , Huyong Lee , TaekSoo Jeon , Sangjin Hyun
IPC: H01L29/06 , H01L29/43 , H01L29/49 , H01L27/092 , H01L29/423
Abstract: A semiconductor device includes a substrate having an active pattern thereon, a gate electrode intersecting the active pattern, and a spacer on a sidewall of the gate electrode. The gate electrode includes a first metal pattern adjacent to the active pattern. The first metal pattern has a first portion parallel to the sidewall and a second portion parallel to the substrate. A top surface of the first portion has a descent in a direction from the spacer towards the second portion.
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公开(公告)号:US09627509B2
公开(公告)日:2017-04-18
申请号:US14802519
申请日:2015-07-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Kyungbum Koo , Wandon Kim , Sangjin Hyun , Shinhye Kim , TaekSoo Jeon , Byung-Suk Jung
IPC: H01L29/66 , H01L29/78 , H01L29/51 , H01L21/768 , H01L21/02
CPC classification number: H01L29/66545 , H01L21/02362 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L29/51 , H01L29/511 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/66636 , H01L29/78 , H01L2029/7858
Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a substrate with an active pattern, a gate electrode provided at the active pattern, and a gate capping structure disposed above the gate electrode. The gate capping structure may include two or more gate capping patterns with different properties from each other, and the use of the gate capping structure makes it possible to form contact plugs in a self-aligned manner and improve operational speed and characteristics of the semiconductor device.
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公开(公告)号:US20180331103A1
公开(公告)日:2018-11-15
申请号:US16017024
申请日:2018-06-25
Applicant: Samsung Electronics Co., Ltd.
Inventor: Wonkeun Chung , Gigwan Park , Huyong Lee , TaekSoo Jeon , Sangjin Hyun
IPC: H01L27/092 , H01L29/06 , H01L29/423
CPC classification number: H01L27/0922 , H01L21/28114 , H01L21/82345 , H01L21/823821 , H01L21/823842 , H01L27/088 , H01L27/092 , H01L27/0924 , H01L29/0649 , H01L29/42364 , H01L29/42376 , H01L29/435 , H01L29/495 , H01L29/4958 , H01L29/4966 , H01L29/66795 , H01L29/785
Abstract: A semiconductor device includes a substrate having an active pattern thereon, a gate electrode intersecting the active pattern, and a spacer on a sidewall of the gate electrode. The gate electrode includes a first metal pattern adjacent to the active pattern. The first metal pattern has a first portion parallel to the sidewall and a second portion parallel to the substrate. A top surface of the first portion has a descent in a direction from the spacer towards the second portion.
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公开(公告)号:US20170186746A1
公开(公告)日:2017-06-29
申请号:US15372876
申请日:2016-12-08
Applicant: Samsung Electronics Co., Ltd.
Inventor: Wonkeun Chung , Gigwan Park , Huyong Lee , TaekSoo Jeon , Sangjin Hyun
IPC: H01L27/092 , H01L29/423 , H01L29/06
CPC classification number: H01L27/0922 , H01L21/82345 , H01L21/823842 , H01L27/088 , H01L27/092 , H01L29/0649 , H01L29/42364 , H01L29/42376 , H01L29/435 , H01L29/495 , H01L29/4958 , H01L29/4966 , H01L29/785
Abstract: A semiconductor device includes a substrate having an active pattern thereon, a gate electrode intersecting the active pattern, and a spacer on a sidewall of the gate electrode. The gate electrode includes a first metal pattern adjacent to the active pattern. The first metal pattern has a first portion parallel to the sidewall and a second portion parallel to the substrate. A top surface of the first portion has a descent in a direction from the spacer towards the second portion.
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