公开(公告)号：US09478486B2

公开(公告)日：2016-10-25

申请号：US14267777

申请日：2014-05-01

Applicant: STATS ChipPAC, Ltd.

Inventor： Sun Mi Kim ,  OhHan Kim ,  KyungHoon Lee

IPC: H01L25/00 ,  H01L23/498 ,  H01L21/683 ,  H01L23/48 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H01L25/03 ,  H01L25/16 ,  H01L23/50 ,  H01L23/00

CPC classification number: H01L23/49833 ,  H01L21/6835 ,  H01L23/481 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/25 ,  H01L24/29 ,  H01L24/48 ,  H01L24/73 ,  H01L24/96 ,  H01L25/03 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/056 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/12105 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/24195 ,  H01L2224/2518 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83805 ,  H01L2224/85411 ,  H01L2224/85424 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/1005 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/13111 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A semiconductor device has a core semiconductor device with a through silicon via (TSV). The core semiconductor device includes a plurality of stacked semiconductor die and semiconductor component. An insulating layer is formed around the core semiconductor device. A conductive via is formed through the insulating layer. A first interconnect structure is formed over a first side of the core semiconductor device. The first interconnect structure is electrically connected to the TSV. A second interconnect structure is formed over a second side of the core semiconductor device. The second interconnect structure is electrically connected to the TSV. The first and second interconnect structures include a plurality of conductive layers separated by insulating layers. A semiconductor die is mounted to the first interconnect structure. The semiconductor die is electrically connected to the core semiconductor device through the first and second interconnect structures and TSV.

Abstract translation: 半导体器件具有带有硅通孔（TSV）的核心半导体器件。 核心半导体器件包括多个堆叠的半导体管芯和半导体部件。 在芯半导体器件周围形成绝缘层。 通过绝缘层形成导电通孔。 在芯半导体器件的第一侧上形成第一互连结构。 第一互连结构电连接到TSV。 在芯半导体器件的第二侧上形成第二互连结构。 第二互连结构电连接到TSV。 第一和第二互连结构包括由绝缘层分开的多个导电层。 半导体管芯安装到第一互连结构。 半导体管芯通过第一和第二互连结构和TSV电连接到芯半导体器件。

公开(公告)号：US20140239509A1

公开(公告)日：2014-08-28

申请号：US14267777

申请日：2014-05-01

Applicant: STATS ChipPAC, Ltd.

Inventor： Sun Mi Kim ,  OhHan Kim ,  KyungHoon Lee

IPC: H01L23/48 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L23/49833 ,  H01L21/6835 ,  H01L23/481 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/25 ,  H01L24/29 ,  H01L24/48 ,  H01L24/73 ,  H01L24/96 ,  H01L25/03 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/056 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/12105 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/24195 ,  H01L2224/2518 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83805 ,  H01L2224/85411 ,  H01L2224/85424 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/1005 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/13111 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A semiconductor device has a core semiconductor device with a through silicon via (TSV). The core semiconductor device includes a plurality of stacked semiconductor die and semiconductor component. An insulating layer is formed around the core semiconductor device. A conductive via is formed through the insulating layer. A first interconnect structure is formed over a first side of the core semiconductor device. The first interconnect structure is electrically connected to the TSV. A second interconnect structure is formed over a second side of the core semiconductor device. The second interconnect structure is electrically connected to the TSV. The first and second interconnect structures include a plurality of conductive layers separated by insulating layers. A semiconductor die is mounted to the first interconnect structure. The semiconductor die is electrically connected to the core semiconductor device through the first and second interconnect structures and TSV.

Abstract translation: 半导体器件具有带有硅通孔（TSV）的核心半导体器件。 核心半导体器件包括多个堆叠的半导体管芯和半导体部件。 在芯半导体器件周围形成绝缘层。 通过绝缘层形成导电通孔。 在芯半导体器件的第一侧上形成第一互连结构。 第一互连结构电连接到TSV。 在芯半导体器件的第二侧上形成第二互连结构。 第二互连结构电连接到TSV。 第一和第二互连结构包括由绝缘层分开的多个导电层。 半导体管芯安装到第一互连结构。 半导体管芯通过第一和第二互连结构和TSV电连接到芯半导体器件。

公开(公告)号：US08519536B2

公开(公告)日：2013-08-27

申请号：US13691427

申请日：2012-11-30

Applicant: STATS ChipPAC, Ltd.

Inventor： KiYoun Jang ,  DaeSik Choi ,  OhHan Kim ,  DongSoo Moon

IPC: H01L23/48

CPC classification number: H01L21/4853 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/81192 ,  H01L2224/814 ,  H01L2224/81411 ,  H01L2224/81413 ,  H01L2224/81416 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device that has a flipchip semiconductor die and substrate. A first insulating layer is formed over the substrate. A via is formed through the first insulating layer. Conductive material is deposited in the via to form a conductive pillar or stacked stud bumps. The conductive pillar is electrically connected to a conductive layer within the substrate. A second insulating layer is formed over the first insulating layer. Bump material is formed over the conductive pillar. The bump material is reflowed to form a bump. The first and second insulating layers are removed. The semiconductor die is mounted to the substrate by reflowing the bump to a conductive layer of the die. The semiconductor die also has a third insulating layer formed over the conductive layer and an active surface of the die and UBM formed over the first conductive layer and third insulating layer.

Abstract translation: 一种具有倒装芯片半导体管芯和衬底的半导体器件。 在衬底上形成第一绝缘层。 通过第一绝缘层形成通孔。 导电材料沉积在通孔中以形成导电柱或堆叠的柱状凸块。 导电柱与衬底内的导电层电连接。 在第一绝缘层上形成第二绝缘层。 凸起材料形成在导电柱上。 凸块材料被回流以形成凸块。 去除第一和第二绝缘层。 半导体管芯通过将凸块回流到管芯的导电层而安装到衬底上。 半导体管芯还具有形成在导电层上的第三绝缘层和形成在第一导电层和第三绝缘层上的管芯和UBM的有源表面。

公开(公告)号：US09543258B2

公开(公告)日：2017-01-10

申请号：US15011311

申请日：2016-01-29

Applicant: STATS ChipPAC, Ltd.

Inventor： OhHan Kim ,  SunMi Kim ,  KyungHoon Lee

IPC: H01L23/60 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H01L23/552 ,  H01L23/00

CPC classification number: H01L23/60 ,  H01L21/561 ,  H01L21/563 ,  H01L23/29 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/552 ,  H01L24/97 ,  H01L2224/05026 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A semiconductor device includes a multi-layer substrate. A ground shield is disposed between layers of the substrate and electrically connected to a ground point. A plurality of semiconductor die is mounted to the substrate over the ground shield. The ground shield extends beyond a footprint of the plurality of semiconductor die. An encapsulant is formed over the plurality of semiconductor die and substrate. Dicing channels are formed in the encapsulant, between the plurality of semiconductor die, and over the ground shield. A plurality of metal-filled holes is formed along the dicing channels, and extends into the substrate and through the ground shield. A top shield is formed over the plurality of semiconductor die and electrically and mechanically connects to the ground shield through the metal-filled holes. The top and ground shields are configured to block electromagnetic interference generated with respect to an integrated passive device disposed in the semiconductor die.

Abstract translation: 半导体器件包括多层衬底。 接地屏蔽层设置在基板的层之间并且电连接到接地点。 多个半导体管芯通过接地屏蔽件安装到衬底上。 接地护罩延伸超过多个半导体管芯的覆盖区。 在多个半导体管芯和衬底上形成密封剂。 切割通道形成在密封剂中，在多个半导体管芯之间，并在接地屏蔽层之上。 沿着切割通道形成多个金属填充的孔，并延伸到基板中并通过接地屏蔽。 在多个半导体管芯上形成顶部屏蔽，并通过金属填充的孔电连接和机械地连接到接地屏蔽层。 顶部和接地屏蔽被配置为阻止相对于设置在半导体管芯中的集成无源器件产生的电磁干扰。

公开(公告)号：US09279673B2

公开(公告)日：2016-03-08

申请号：US13846593

申请日：2013-03-18

Applicant: STATS ChipPAC, Ltd.

Inventor： WonJun Ko ,  SeungYong Chai ,  OhHan Kim ,  GwangTae Kim ,  Kenny Lee

IPC: G01K15/00 ,  G01N25/72 ,  G01N3/20 ,  G01B11/30 ,  H01L21/66

CPC classification number: G01B11/306 ,  H01L22/12

Abstract: A warpage test system uses a calibration block to calibrate the warpage test system over a temperature profile. The calibration block includes a first metal block bonded to a second metal block. The first metal block includes a first metal and a second different metal. The first metal block includes a CTE different than a CTE of the second metal block. The calibration block is disposed in the warpage test system. A warpage of the calibration block is measured over a temperature profile ranging from 28° C. to 260° C. A deviation between the measured warpage of the calibration block and a known thermal expansion of the calibration block over the temperature profile is recorded. The warpage measurement in a semiconductor package is compensated by the deviation between the measured warpage of the calibration block and the known thermal expansion or warpage of the calibration block over the temperature profile.

Abstract translation: 翘曲测试系统使用校准块在温度曲线上校准翘曲测试系统。 校准块包括结合到第二金属块的第一金属块。 第一金属块包括第一金属和第二不同的金属。 第一金属块包括与第二金属块的CTE不同的CTE。 校准块设置在翘曲测试系统中。 在28℃至260℃的温度曲线上测量校准块的翘曲。记录校准块的测量翘曲与校准块在温度曲线上的已知热膨胀之间的偏差。 半导体封装中的翘曲测量通过校准块的测量翘曲与校准块在温度曲线上的已知热膨胀或翘曲之间的偏差来补偿。

公开(公告)号：US20130154090A1

公开(公告)日：2013-06-20

申请号：US13768862

申请日：2013-02-15

Applicant: STATS ChipPAC, Ltd.

Inventor： DaeSik Choi ,  OhHan Kim ,  SungWon Cho

IPC: H01L21/56 ,  H01L23/498

CPC classification number: H01L23/522 ,  H01L21/565 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/82 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05555 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11831 ,  H01L2224/11903 ,  H01L2224/11906 ,  H01L2224/13011 ,  H01L2224/13012 ,  H01L2224/13019 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81345 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/00

Abstract: A semiconductor device has a substrate and first conductive pads formed over the substrate. An interconnect surface area of the first conductive pads is expanded by forming a plurality of recesses into the first conductive pads. The recesses can be an arrangement of concentric rings, arrangement of circular recesses, or arrangement of parallel linear trenches. Alternatively, the interconnect surface area of the first conductive pads is expanded by forming a second conductive pad over the first conductive pad. A semiconductor die has a plurality of interconnect structures formed over a surface of the semiconductor die. The semiconductor die is mounted to the substrate with the interconnect structures contacting the expanded interconnect surface area of the first conductive pads to increase bonding strength of the interconnect structure to the first conductive pads. A mold underfill material is deposited between the semiconductor die and substrate.

Abstract translation: 半导体器件具有衬底和形成在衬底上的第一导电焊盘。 通过在第一导电焊盘中形成多个凹槽来扩展第一导电焊盘的互连表面积。 凹槽可以是同心环的布置，圆形凹槽的布置或平行的线性沟槽的布置。 或者，通过在第一导电焊盘上形成第二导电焊盘来扩展第一导电焊盘的互连表面积。 半导体管芯具有形成在半导体管芯的表面上的多个互连结构。 半导体管芯安装到衬底上，互连结构接触第一导电焊盘的扩展互连表面区域，以增加互连结构与第一导电焊盘的接合强度。 模具底部填充材料沉积在半导体管芯和衬底之间。

公开(公告)号：US09373578B2

公开(公告)日：2016-06-21

申请号：US14192706

申请日：2014-02-27

Applicant: STATS ChipPAC, Ltd.

Inventor： DaeSik Choi ,  OhHan Kim ,  SungWon Cho

IPC: H01L21/44 ,  H01L23/52 ,  H01L23/522 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/522 ,  H01L21/565 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/82 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05555 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11831 ,  H01L2224/11903 ,  H01L2224/11906 ,  H01L2224/13011 ,  H01L2224/13012 ,  H01L2224/13019 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81345 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/00

Abstract: A semiconductor device has a substrate and first conductive pads formed over the substrate. An interconnect surface area of the first conductive pads is expanded by forming a plurality of recesses into the first conductive pads. The recesses can be an arrangement of concentric rings, arrangement of circular recesses, or arrangement of parallel linear trenches. Alternatively, the interconnect surface area of the first conductive pads is expanded by forming a second conductive pad over the first conductive pad. A semiconductor die has a plurality of interconnect structures formed over a surface of the semiconductor die. The semiconductor die is mounted to the substrate with the interconnect structures contacting the expanded interconnect surface area of the first conductive pads to increase bonding strength of the interconnect structure to the first conductive pads. A mold underfill material is deposited between the semiconductor die and substrate.

公开(公告)号：US20160148882A1

公开(公告)日：2016-05-26

申请号：US15011311

申请日：2016-01-29

Applicant: STATS ChipPAC, Ltd.

Inventor： OhHan Kim ,  SunMi Kim ,  KyungHoon Lee

IPC: H01L23/60 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/60 ,  H01L21/561 ,  H01L21/563 ,  H01L23/29 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/552 ,  H01L24/97 ,  H01L2224/05026 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A semiconductor device includes a multi-layer substrate. A ground shield is disposed between layers of the substrate and electrically connected to a ground point. A plurality of semiconductor die is mounted to the substrate over the ground shield. The ground shield extends beyond a footprint of the plurality of semiconductor die. An encapsulant is formed over the plurality of semiconductor die and substrate. Dicing channels are formed in the encapsulant, between the plurality of semiconductor die, and over the ground shield. A plurality of metal-filled holes is formed along the dicing channels, and extends into the substrate and through the ground shield. A top shield is formed over the plurality of semiconductor die and electrically and mechanically connects to the ground shield through the metal-filled holes. The top and ground shields are configured to block electromagnetic interference generated with respect to an integrated passive device disposed in the semiconductor die.

Abstract translation: 半导体器件包括多层衬底。 接地屏蔽层设置在基板的层之间并且电连接到接地点。 多个半导体管芯通过接地屏蔽件安装到衬底上。 接地护罩延伸超过多个半导体管芯的覆盖区。 在多个半导体管芯和衬底上形成密封剂。 切割通道形成在密封剂中，在多个半导体管芯之间，并在接地屏蔽层之上。 沿着切割通道形成多个金属填充的孔，并延伸到基板中并通过接地屏蔽。 在多个半导体管芯上形成顶部屏蔽，并通过金属填充的孔电连接和机械地连接到接地屏蔽层。 顶部和接地屏蔽被配置为阻止相对于设置在半导体管芯中的集成无源器件产生的电磁干扰。

公开(公告)号：US20130264705A1

公开(公告)日：2013-10-10

申请号：US13906844

申请日：2013-05-31

Applicant: STATS ChipPAC, Ltd.

Inventor： KiYoun Jang ,  DaeSik Choi ,  OhHan Kim ,  DongSoo Moon

IPC: H01L21/48 ,  H01L23/498

CPC classification number: H01L21/4853 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/81192 ,  H01L2224/814 ,  H01L2224/81411 ,  H01L2224/81413 ,  H01L2224/81416 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device that has a flipchip semiconductor die and substrate. A first insulating layer is formed over the substrate. A via is formed through the first insulating layer. Conductive material is deposited in the via to form a conductive pillar or stacked stud bumps. The conductive pillar is electrically connected to a conductive layer within the substrate. A second insulating layer is formed over the first insulating layer. Bump material is formed over the conductive pillar. The bump material is reflowed to form a bump. The first and second insulating layers are removed. The semiconductor die is mounted to the substrate by reflowing the bump to a conductive layer of the die. The semiconductor die also has a third insulating layer formed over the conductive layer and an active surface of the die and UBM formed over the first conductive layer and third insulating layer.

Abstract translation: 一种具有倒装芯片半导体管芯和衬底的半导体器件。 在衬底上形成第一绝缘层。 通过第一绝缘层形成通孔。 导电材料沉积在通孔中以形成导电柱或堆叠的柱状凸块。 导电柱与衬底内的导电层电连接。 在第一绝缘层上形成第二绝缘层。 凸起材料形成在导电柱上。 凸块材料被回流以形成凸块。 去除第一和第二绝缘层。 半导体管芯通过将凸块回流到管芯的导电层而安装到衬底上。 半导体管芯还具有形成在导电层上的第三绝缘层和形成在第一导电层和第三绝缘层上的管芯和UBM的有源表面。

公开(公告)号：US20140269810A1

公开(公告)日：2014-09-18

申请号：US13846593

申请日：2013-03-18

Applicant: STATS CHIPPAC, LTD.

Inventor： WonJun Ko ,  SeungYong Chai ,  OhHan Kim ,  GwangTae Kim ,  Kenny Lee

IPC: G01N25/72

CPC classification number: G01B11/306 ,  H01L22/12

Abstract: A warpage test system uses a calibration block to calibrate the warpage test system over a temperature profile. The calibration block includes a first metal block bonded to a second metal block. The first metal block includes a first metal and a second different metal. The first metal block includes a CTE different than a CTE of the second metal block. The calibration block is disposed in the warpage test system. A warpage of the calibration block is measured over a temperature profile ranging from 28° C. to 260° C. A deviation between the measured warpage of the calibration block and a known thermal expansion of the calibration block over the temperature profile is recorded. The warpage measurement in a semiconductor package is compensated by the deviation between the measured warpage of the calibration block and the known thermal expansion or warpage of the calibration block over the temperature profile.

Abstract translation: 翘曲测试系统使用校准块在温度曲线上校准翘曲测试系统。 校准块包括结合到第二金属块的第一金属块。 第一金属块包括第一金属和第二不同的金属。 第一金属块包括与第二金属块的CTE不同的CTE。 校准块设置在翘曲测试系统中。 在28℃至260℃的温度曲线上测量校准块的翘曲。记录校准块的测量翘曲与校准块在温度曲线上的已知热膨胀之间的偏差。 半导体封装中的翘曲测量通过校准块的测量翘曲与校准块在温度曲线上的已知热膨胀或翘曲之间的偏差来补偿。