公开(公告)号：US08896133B2

公开(公告)日：2014-11-25

申请号：US13870928

申请日：2013-04-25

Applicant: STATS ChipPAC, Ltd.

Inventor： SungWon Cho ,  KiYoun Jang ,  YongHee Kang ,  Hyung Sang Park

IPC: H01L23/48 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56

CPC classification number: H01L24/09 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/1155 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/11903 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17104 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48158 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81011 ,  H01L2224/81022 ,  H01L2224/81024 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/8385 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3841 ,  H01L2924/01014 ,  H01L2924/0105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a first substrate and first conductive pillars formed over the first substrate. Second conductive pillars are formed over the first substrate alternating with the first conductive pillars. The second conductive pillars are vertically offset with respect to the first conductive pillars. First BOT interconnect sites are formed over a second substrate. Second BOT interconnect sites are formed over the second substrate alternating with the first interconnect sites. The second interconnect sites are vertically offset with respect to the first interconnect sites. The first substrate is mounted to the second substrate such that the first conductive pillars are aligned with and electrically connected to the first interconnect sites and the second conductive pillars are aligned with and electrically connected to the second interconnect sites. An underfill material is deposited between the first and second substrates. The first substrate can be a flipchip type semiconductor device.

Abstract translation: 半导体器件具有形成在第一衬底上的第一衬底和第一导电柱。 第二导电柱形成在第一基板上，与第一导电柱交替。 第二导电柱相对于第一导电柱垂直偏移。 第一BOT互连位点形成在第二基底上。 第二BOT互连位置形成在第二衬底上与第一互连位置交替。 第二互连站点相对于第一互连站点垂直偏移。 第一衬底安装到第二衬底，使得第一导电柱与第一互连位置对准并电连接，并且第二导电柱与第二互连位置对准并电连接到第二互连位置。 底部填充材料沉积在第一和第二基底之间。 第一基板可以是倒装芯片型半导体器件。

公开(公告)号：US09780063B2

公开(公告)日：2017-10-03

申请号：US14328922

申请日：2014-07-11

Applicant: STATS ChipPAC, Ltd.

Inventor： JoonYoung Choi ,  YoungJoon Kim ,  SungWon Cho

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/97 ,  H01L2224/02126 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/03903 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/05073 ,  H01L2224/0508 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05552 ,  H01L2224/05558 ,  H01L2224/05566 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/10126 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13007 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13076 ,  H01L2224/136 ,  H01L2224/13611 ,  H01L2224/13613 ,  H01L2224/13616 ,  H01L2224/13624 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/81805

Abstract: A semiconductor wafer has a plurality of semiconductor die with contact pads for electrical interconnect. An insulating layer is formed over the semiconductor wafer. A bump structure is formed over the contact pads. The bump structure has a buffer layer formed over the insulating layer and contact pad. A portion of the buffer layer is removed to expose the contact pad and an outer portion of the insulating layer. A UBM layer is formed over the buffer layer and contact pad. The UBM layer follows a contour of the buffer layer and contact pad. A ring-shaped conductive pillar is formed over the UBM layer using a patterned photoresist layer filled with electrically conductive material. A conductive barrier layer is formed over the ring-shaped conductive pillar. A bump is formed over the conductive barrier layer. The buffer layer reduces thermal and mechanical stress on the bump and contact pad.

公开(公告)号：US20140319680A1

公开(公告)日：2014-10-30

申请号：US14328922

申请日：2014-07-11

Applicant: STATS ChipPAC, Ltd.

Inventor： JoonYoung Choi ,  YoungJoon Kim ,  SungWon Cho

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/97 ,  H01L2224/02126 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/03903 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/05073 ,  H01L2224/0508 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05552 ,  H01L2224/05558 ,  H01L2224/05566 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/10126 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13007 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13076 ,  H01L2224/136 ,  H01L2224/13611 ,  H01L2224/13613 ,  H01L2224/13616 ,  H01L2224/13624 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/01082 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/81805

Abstract: A semiconductor wafer has a plurality of semiconductor die with contact pads for electrical interconnect. An insulating layer is formed over the semiconductor wafer. A bump structure is formed over the contact pads. The bump structure has a buffer layer formed over the insulating layer and contact pad. A portion of the buffer layer is removed to expose the contact pad and an outer portion of the insulating layer. A UBM layer is formed over the buffer layer and contact pad. The UBM layer follows a contour of the buffer layer and contact pad. A ring-shaped conductive pillar is formed over the UBM layer using a patterned photoresist layer filled with electrically conductive material. A conductive barrier layer is formed over the ring-shaped conductive pillar. A bump is formed over the conductive barrier layer. The buffer layer reduces thermal and mechanical stress on the bump and contact pad.

Abstract translation: 半导体晶片具有多个具有用于电互连的接触焊盘的半导体管芯。 在半导体晶片上形成绝缘层。 在接触焊盘上形成凸块结构。 凸块结构具有形成在绝缘层和接触垫上的缓冲层。 去除缓冲层的一部分以暴露接触焊盘和绝缘层的外部部分。 在缓冲层和接触垫上形成UBM层。 UBM层遵循缓冲层和接触垫的轮廓。 使用填充有导电材料的图案化光致抗蚀剂层在UBM层之上形成环形导电柱。 导电阻挡层形成在环形导电柱上。 在导电阻挡层上形成凸块。 缓冲层减少凸块和接触垫上的热应力和机械应力。

公开(公告)号：US20140008783A1

公开(公告)日：2014-01-09

申请号：US14021740

申请日：2013-09-09

Applicant: STATS ChipPAC, Ltd.

Inventor： SungWon Cho ,  TaeWoo Lee ,  DaeSik Choi ,  KyuWon Lee

IPC: H01L23/48

CPC classification number: H01L23/48 ,  H01L24/05 ,  H01L24/16 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/05568 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/165 ,  H01L2224/29 ,  H01L2224/29099 ,  H01L2224/29101 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29298 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81101 ,  H01L2224/81193 ,  H01L2224/83889 ,  H01L2224/92125 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/01083 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/05552 ,  H01L2224/81805

Abstract: A semiconductor device has a flipchip type semiconductor die with contact pads and substrate with contact pads. A flux material is deposited over the contact pads of the semiconductor die and contact pads of the substrate. A solder tape formed as a continuous body of solder material with a plurality of recesses is disposed between the contact pads of the semiconductor die and substrate. The solder tape is brought to a liquidus state to separate a portion of the solder tape outside a footprint of the contact pads of the semiconductor die and substrate under surface tension and coalesce the solder material as an electrical interconnect substantially within the footprint of the contact pads of the semiconductor die and substrate. The contact pads on the semiconductor die and substrate can be formed with an extension or recess to increase surface area of the contact pads.

Abstract translation: 半导体器件具有带有接触焊盘和具有接触焊盘的衬底的倒装芯片型半导体管芯。 焊剂材料沉积在半导体管芯的接触焊盘和衬底的接触焊盘上。 形成为具有多个凹部的焊料材料的连续体的焊料带设置在半导体管芯和衬底的接触焊盘之间。 焊带被带到液相线状态，以将表面张力下的半导体管芯和衬底的接触焊盘的一部分焊接区分隔开，并将焊料材料作为基本上在接触焊盘的覆盖区内的电互连 的半导体管芯和衬底。 半导体管芯和衬底上的接触焊盘可以形成有延伸部或凹部，以增加接触焊盘的表面积。

公开(公告)号：US20130234324A1

公开(公告)日：2013-09-12

申请号：US13870928

申请日：2013-04-25

Applicant: STATS CHIPPAC, LTD.

Inventor： SungWon Cho ,  KiYoun Jang ,  YongHee Kang ,  Hyung Sang Park

IPC: H01L23/00

CPC classification number: H01L24/09 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/1155 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/11903 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17104 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48158 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81011 ,  H01L2224/81022 ,  H01L2224/81024 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/8385 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3841 ,  H01L2924/01014 ,  H01L2924/0105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a first substrate and first conductive pillars formed over the first substrate. Second conductive pillars are formed over the first substrate alternating with the first conductive pillars. The second conductive pillars are vertically offset with respect to the first conductive pillars. First BOT interconnect sites are formed over a second substrate. Second BOT interconnect sites are formed over the second substrate alternating with the first interconnect sites. The second interconnect sites are vertically offset with respect to the first interconnect sites. The first substrate is mounted to the second substrate such that the first conductive pillars are aligned with and electrically connected to the first interconnect sites and the second conductive pillars are aligned with and electrically connected to the second interconnect sites. An underfill material is deposited between the first and second substrates. The first substrate can be a flipchip type semiconductor device.

Abstract translation: 半导体器件具有形成在第一衬底上的第一衬底和第一导电柱。 第二导电柱形成在第一基板上，与第一导电柱交替。 第二导电柱相对于第一导电柱垂直偏移。 第一BOT互连位点形成在第二基底上。 第二BOT互连位置形成在第二衬底上与第一互连位置交替。 第二互连站点相对于第一互连站点垂直偏移。 第一衬底安装到第二衬底，使得第一导电柱与第一互连位置对准并电连接，并且第二导电柱与第二互连位置对准并电连接到第二互连位置。 底部填充材料沉积在第一和第二基底之间。 第一基板可以是倒装芯片型半导体器件。

公开(公告)号：US20130154090A1

公开(公告)日：2013-06-20

申请号：US13768862

申请日：2013-02-15

Applicant: STATS ChipPAC, Ltd.

Inventor： DaeSik Choi ,  OhHan Kim ,  SungWon Cho

IPC: H01L21/56 ,  H01L23/498

CPC classification number: H01L23/522 ,  H01L21/565 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/82 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05555 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11831 ,  H01L2224/11903 ,  H01L2224/11906 ,  H01L2224/13011 ,  H01L2224/13012 ,  H01L2224/13019 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81345 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/00

Abstract: A semiconductor device has a substrate and first conductive pads formed over the substrate. An interconnect surface area of the first conductive pads is expanded by forming a plurality of recesses into the first conductive pads. The recesses can be an arrangement of concentric rings, arrangement of circular recesses, or arrangement of parallel linear trenches. Alternatively, the interconnect surface area of the first conductive pads is expanded by forming a second conductive pad over the first conductive pad. A semiconductor die has a plurality of interconnect structures formed over a surface of the semiconductor die. The semiconductor die is mounted to the substrate with the interconnect structures contacting the expanded interconnect surface area of the first conductive pads to increase bonding strength of the interconnect structure to the first conductive pads. A mold underfill material is deposited between the semiconductor die and substrate.

Abstract translation: 半导体器件具有衬底和形成在衬底上的第一导电焊盘。 通过在第一导电焊盘中形成多个凹槽来扩展第一导电焊盘的互连表面积。 凹槽可以是同心环的布置，圆形凹槽的布置或平行的线性沟槽的布置。 或者，通过在第一导电焊盘上形成第二导电焊盘来扩展第一导电焊盘的互连表面积。 半导体管芯具有形成在半导体管芯的表面上的多个互连结构。 半导体管芯安装到衬底上，互连结构接触第一导电焊盘的扩展互连表面区域，以增加互连结构与第一导电焊盘的接合强度。 模具底部填充材料沉积在半导体管芯和衬底之间。

公开(公告)号：US20140175642A1

公开(公告)日：2014-06-26

申请号：US14192706

申请日：2014-02-27

Applicant: STATS ChipPAC, Ltd.

Inventor： DaeSik Choi ,  OhHan Kim ,  SungWon Cho

IPC: H01L23/522 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/522 ,  H01L21/565 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/82 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05555 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11831 ,  H01L2224/11903 ,  H01L2224/11906 ,  H01L2224/13011 ,  H01L2224/13012 ,  H01L2224/13019 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81345 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/00

Abstract: A semiconductor device has a substrate and first conductive pads formed over the substrate. An interconnect surface area of the first conductive pads is expanded by forming a plurality of recesses into the first conductive pads. The recesses can be an arrangement of concentric rings, arrangement of circular recesses, or arrangement of parallel linear trenches. Alternatively, the interconnect surface area of the first conductive pads is expanded by forming a second conductive pad over the first conductive pad. A semiconductor die has a plurality of interconnect structures formed over a surface of the semiconductor die. The semiconductor die is mounted to the substrate with the interconnect structures contacting the expanded interconnect surface area of the first conductive pads to increase bonding strength of the interconnect structure to the first conductive pads. A mold underfill material is deposited between the semiconductor die and substrate.

Abstract translation: 半导体器件具有衬底和形成在衬底上的第一导电焊盘。 通过在第一导电焊盘中形成多个凹槽来扩展第一导电焊盘的互连表面积。 凹槽可以是同心环的布置，圆形凹槽的布置或平行的线性沟槽的布置。 或者，通过在第一导电焊盘上形成第二导电焊盘来扩展第一导电焊盘的互连表面积。 半导体管芯具有在半导体管芯的表面上形成的多个互连结构。 半导体管芯安装到衬底上，互连结构接触第一导电焊盘的扩展互连表面区域，以增加互连结构与第一导电焊盘的接合强度。 模具底部填充材料沉积在半导体管芯和衬底之间。

公开(公告)号：US08709935B2

公开(公告)日：2014-04-29

申请号：US13768862

申请日：2013-02-15

Applicant: STATS ChipPAC, Ltd.

Inventor： DaeSik Choi ,  OhHan Kim ,  SungWon Cho

IPC: H01L21/44 ,  H01L21/50 ,  H01L23/52 ,  H01L23/48 ,  H01L23/485 ,  H01L23/498

CPC classification number: H01L23/522 ,  H01L21/565 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/82 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05555 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11831 ,  H01L2224/11903 ,  H01L2224/11906 ,  H01L2224/13011 ,  H01L2224/13012 ,  H01L2224/13019 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81345 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/00

Abstract: A semiconductor device has a substrate and first conductive pads formed over the substrate. An interconnect surface area of the first conductive pads is expanded by forming a plurality of recesses into the first conductive pads. The recesses can be an arrangement of concentric rings, arrangement of circular recesses, or arrangement of parallel linear trenches. Alternatively, the interconnect surface area of the first conductive pads is expanded by forming a second conductive pad over the first conductive pad. A semiconductor die has a plurality of interconnect structures formed over a surface of the semiconductor die. The semiconductor die is mounted to the substrate with the interconnect structures contacting the expanded interconnect surface area of the first conductive pads to increase bonding strength of the interconnect structure to the first conductive pads. A mold underfill material is deposited between the semiconductor die and substrate.

Abstract translation: 半导体器件具有衬底和形成在衬底上的第一导电焊盘。 通过在第一导电焊盘中形成多个凹槽来扩展第一导电焊盘的互连表面积。 凹槽可以是同心环的布置，圆形凹槽的布置或平行的线性沟槽的布置。 或者，通过在第一导电焊盘上形成第二导电焊盘来扩展第一导电焊盘的互连表面积。 半导体管芯具有形成在半导体管芯的表面上的多个互连结构。 半导体管芯安装到衬底上，互连结构接触第一导电焊盘的扩展互连表面区域，以增加互连结构与第一导电焊盘的接合强度。 模具底部填充材料沉积在半导体管芯和衬底之间。

公开(公告)号：US09373578B2

公开(公告)日：2016-06-21

申请号：US14192706

申请日：2014-02-27

Applicant: STATS ChipPAC, Ltd.

Inventor： DaeSik Choi ,  OhHan Kim ,  SungWon Cho

IPC: H01L21/44 ,  H01L23/52 ,  H01L23/522 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/522 ,  H01L21/565 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/82 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05555 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11831 ,  H01L2224/11903 ,  H01L2224/11906 ,  H01L2224/13011 ,  H01L2224/13012 ,  H01L2224/13019 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81345 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/00

Abstract: A semiconductor device has a substrate and first conductive pads formed over the substrate. An interconnect surface area of the first conductive pads is expanded by forming a plurality of recesses into the first conductive pads. The recesses can be an arrangement of concentric rings, arrangement of circular recesses, or arrangement of parallel linear trenches. Alternatively, the interconnect surface area of the first conductive pads is expanded by forming a second conductive pad over the first conductive pad. A semiconductor die has a plurality of interconnect structures formed over a surface of the semiconductor die. The semiconductor die is mounted to the substrate with the interconnect structures contacting the expanded interconnect surface area of the first conductive pads to increase bonding strength of the interconnect structure to the first conductive pads. A mold underfill material is deposited between the semiconductor die and substrate.