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    PHASE-CHANGE MEMORY DEVICE HAVING PHASE-CHANGE REGION DIVIDED INTO MULTI LAYERS AND OPERATING METHOD THEREOF
    2.
    发明申请
    PHASE-CHANGE MEMORY DEVICE HAVING PHASE-CHANGE REGION DIVIDED INTO MULTI LAYERS AND OPERATING METHOD THEREOF 审中-公开
    具有相变区域的相变存储器件分为多层及其操作方法

    公开(公告)号：US20160072059A1

    公开(公告)日：2016-03-10

    申请号：US14941208

    申请日：2015-11-13

    申请人： SK hynix Inc.

    发明人： Jin Hyock KIM ,  Su Jin CHAE ,  Young Seok KWON ,  Hae Chan PARK

    IPC分类号： H01L45/00 ,  G11C13/00

    CPC分类号： H01L45/06 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0092 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1683

    摘要： A phase-change memory device including a phase-change region divided into multi layers and an operation method thereof are provided. The device includes a first phase-change layer to which a current is provided from a heating electrode, and a second phase-change layer formed with continuity to the first phase-change layer and having a different width from the first phase-change layer, and to which a current is provided from the heating electrode. The first and second phase-change layers include materials selected from a first group consisting of GeTe, GST415, GST315, GST225, GST124, GST147, and GST172 or a second group consisting of InSbSe, SnGeSe, GST, SnSbSe, and SiSbSe. The second phase-change layer includes a material different from the first phase-change layer, which is selected from the same group as the first phase-change layer and has smaller resistivity than the first phase-change layer.

    摘要翻译： 提供一种包括分为多层的相变区域的相变存储器件及其操作方法。 该装置包括从加热电极提供电流的第一相变层和与第一相变层连续形成并且具有与第一相变层不同的宽度的第二相变层， 并且从加热电极提供电流。 第一和第二相变层包括从由GeTe，GST415，GST315，GST225，GST124，GST147和GST172组成的第一组中选择的材料或由InSbSe，SnGeSe，GST，SnSbSe和SiSbSe组成的第二组的材料。 第二相变层包括与第一相变层不同的材料，其选自与第一相变层相同的组，并且具有比第一相变层更小的电阻率。

    3D SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME
    5.
    发明申请
    3D SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    3D半导体集成电路装置及其制造方法

    公开(公告)号：US20160042960A1

    公开(公告)日：2016-02-11

    申请号：US14540866

    申请日：2014-11-13

    申请人： SK hynix Inc.

    发明人： Jin Ha KIM ,  Jun Kwan KIM ,  Kang Sik CHOI ,  Su Jin CHAE ,  Young Ho LEE

    IPC分类号： H01L21/285 ,  H01L29/78 ,  H01L29/45 ,  H01L27/24

    CPC分类号： H01L29/7827 ,  H01L21/28518 ,  H01L21/28531 ,  H01L21/76843 ,  H01L21/76855 ,  H01L27/2454 ,  H01L29/456

    摘要： A 3D semiconductor integrated circuit device and a method of manufacturing the same are provided. An active pillar is formed on a semiconductor substrate, and an interlayer insulating layer is formed so that the active pillar is buried in the interlayer insulating layer. The interlayer insulating layer is etched to form a hole so that the active pillar and a peripheral region of the active pillar are exposed. An etching process is performed on the peripheral region of the active pillar exposed through the hole by a certain depth, and a space having the depth is provided between the active pillar and the interlayer insulating layer. A silicon material layer is formed to be buried in the space having the depth, and an ohmic contact layer is formed on the silicon material layer and the active pillar.

    摘要翻译： 提供了一种3D半导体集成电路器件及其制造方法。 在半导体衬底上形成有源柱，并且形成层间绝缘层，使得有源柱埋在层间绝缘层中。 蚀刻层间绝缘层以形成孔，使得活性柱和活性柱的周边区域露出。 在通过孔暴露一定深度的有源柱的周边区域进行蚀刻处理，并且在有源柱和层间绝缘层之间设置具有深度的空间。 形成硅材料层以埋在具有深度的空间中，并且在硅材料层和有源支柱上形成欧姆接触层。

    METHOD FOR FABRICATING SEMICONDUCTOR APPARATUS
    7.
    发明申请
    METHOD FOR FABRICATING SEMICONDUCTOR APPARATUS 审中-公开
    制作半导体装置的方法

    公开(公告)号：US20150263282A1

    公开(公告)日：2015-09-17

    申请号：US14296133

    申请日：2014-06-04

    申请人： SK Hynix Inc.

    发明人： Yong Hun SUNG ,  Kwon HONG ,  Su Jin CHAE ,  Hyun Seok KANG ,  Ji Won MOON

    IPC分类号： H01L45/00 ,  H01L21/285

    CPC分类号： H01L45/16 ,  H01L21/28518 ,  H01L21/28562 ,  H01L27/2454 ,  H01L45/06 ,  H01L45/1233

    摘要： A method for fabricating a semiconductor apparatus includes setting a semiconductor substrate in a process chamber, increasing an internal temperature of the process chamber to a predetermined temperature for pyrolyzing a source gas, supplying the source gas to the inside of the process chamber and pyrolyzing ions of the source gas to remain on the semiconductor substrate, and forming the ohmic contact layer by supplying a reaction gas to the inside of the process chamber, wherein the reaction gas is reacted with non-metal ions pyrolyzed from source gas.

    摘要翻译： 一种半导体装置的制造方法，其特征在于，在处理室内设置半导体基板，将处理室的内部温度上升到规定温度，使源气体进行热解，将原料气体供给到处理室内部， 源气体保留在半导体衬底上，并通过向处理室的内部提供反应气体形成欧姆接触层，其中反应气体与从源气体热解的非金属离子反应。

    SEMICONDUCTOR MEMORY DEVICE AND FABRICATION METHOD THEREOF
    8.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND FABRICATION METHOD THEREOF 有权
    半导体存储器件及其制造方法

    公开(公告)号：US20140054752A1

    公开(公告)日：2014-02-27

    申请号：US13711804

    申请日：2012-12-12

    申请人： SK HYNIX INC.

    发明人： Su Jin CHAE ,  Jin Hyock KIM ,  Young Seok KWON

    IPC分类号： H01L23/28 ,  H01L21/768

    CPC分类号： H01L45/1683 ,  H01L21/76892 ,  H01L21/76897 ,  H01L23/28 ,  H01L27/2409 ,  H01L43/12 ,  H01L45/06 ,  H01L45/1253 ,  H01L45/16 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor memory device and a fabrication method thereof capable of improving electric contact characteristic between an access device and a lower electrode are provided. The semiconductor memory device includes an access device formed in a pillar shape on a semiconductor substrate, a first conductive layer formed over the access device, a protection layer formed on an edge of the first conductive layer to a predetermined thickness, and a lower electrode connected to the first conductive layer.

    摘要翻译： 提供一种能够提高存取装置与下部电极之间的电接触特性的半导体存储装置及其制造方法。 半导体存储器件包括在半导体衬底上形成为柱状的访问器件，形成在存取器件上的第一导电层，形成在第一导电层的边缘上至预定厚度的保护层，以及连接到第一导电层的下部电极 到第一导电层。