公开(公告)号：US20240014304A1

公开(公告)日：2024-01-11

申请号：US18170104

申请日：2023-02-16

申请人： Samsung Electronics Co., Ltd.

发明人： Kyung Bin Chun ,  Jin Bum Kim ,  Dong Suk Shin ,  Gyeom Kim ,  Da Hye Kim

IPC分类号： H01L29/775 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08

CPC分类号： H01L29/775 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/42392 ,  H01L29/0847

摘要： A semiconductor device includes a lower pattern on a substrate and protruding in a first direction, a source/drain pattern on the lower pattern and including a semiconductor liner film in contact with the lower pattern, and an epitaxial insulating liner extending along at least a portion of a sidewall of the semiconductor liner film, wherein the epitaxial insulating liner is in contact with the semiconductor liner film, wherein the semiconductor liner film includes a first portion, wherein the first portion of the semiconductor liner film includes a first point spaced apart from the lower pattern at a first height, and a second point spaced apart from the lower pattern at a second height, wherein the second height is greater than the first height, wherein a width of the semiconductor liner film in a second direction at the first point is less than a width of the semiconductor liner film in the second direction at the second point, and wherein the epitaxial insulating liner extends along at least a portion of a sidewall of the first portion of the semiconductor liner film.

公开(公告)号：US10128112B2

公开(公告)日：2018-11-13

申请号：US15595945

申请日：2017-05-16

申请人： Samsung Electronics Co., Ltd.

发明人： Cho Eun Lee ,  Jin Bum Kim ,  Kang Hun Moon ,  Jae Myung Choe ,  Sun Jung Kim ,  Dong Suk Shin ,  Il Gyou Shin ,  Jeong Ho Yoo

IPC分类号： H01L21/336 ,  H01L21/02 ,  H01L21/223 ,  H01L29/66

摘要： A method of fabricating a semiconductor device is provided. The method includes forming a dummy gate electrode on a substrate, forming a trench on a side surface of the dummy gate electrode, performing a bake process of removing an impurity from the trench and forming a source/drain in the trench, wherein the bake process comprises a first stage and a second stage following the first stage, an air pressure in which the substrate is disposed during the first stage is different from an air pressure in which the substrate is disposed during the second stage, and the bake process is performed while the substrate is on a stage rotating the substrate, wherein a revolution per minute (RPM) of the substrate during the first stage is different from a revolution per minute (RPM) of the substrate during the second stage.

公开(公告)号：US10784379B2

公开(公告)日：2020-09-22

申请号：US15995414

申请日：2018-06-01

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Seok Hoon Kim ,  Dong Myoung Kim ,  Dong Suk Shin ,  Seung Hun Lee ,  Cho Eun Lee ,  Hyun Jung Lee ,  Sung Uk Jang ,  Edward Nam Kyu Cho ,  Min-Hee Choi

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/02 ,  H01L29/423 ,  H01L29/165 ,  H01L27/088 ,  H01L29/08 ,  H01L29/49 ,  H01L27/12

摘要： A semiconductor device includes a first fin type pattern on a substrate, a second fin type pattern, parallel to the first fin type pattern, on the substrate, and an epitaxial pattern on the first and second fin type patterns. The epitaxial pattern may include a shared semiconductor pattern on the first fin type pattern and the second fin type pattern. The shared semiconductor pattern may include a first sidewall adjacent to the first fin type pattern and a second sidewall adjacent to the second fin type pattern. The first sidewall may include a first lower facet, a first upper facet on the first lower facet and a first connecting curved surface connecting the first lower and upper facets. The second sidewall may include a second lower facet, a second upper facet on the second lower facet and a second connecting curved surface connecting the second lower and upper facets.

公开(公告)号：US20180211959A1

公开(公告)日：2018-07-26

申请号：US15819309

申请日：2017-11-21

申请人： Samsung Electronics Co., Ltd.

发明人： Hyun Kwan Yu ,  Hyo Jin Kim ,  Dong Suk Shin ,  Ji Hye Yi ,  Ryong Ha

IPC分类号： H01L27/092

CPC分类号： H01L27/0924 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/0869 ,  H01L29/0886 ,  H01L29/4238 ,  H01L29/66484 ,  H01L29/66636

摘要： A semiconductor device includes a substrate, first through fourth gate electrodes, and first through fifth fin active pattern. A first recess which is formed in the substrate between the first and second gate electrodes intersecting the second fin active pattern, is filled with a first source/drain region, and has a first depth in a third direction perpendicular to the first and second directions. A second recess which is formed in the substrate between the third and fourth gate electrodes intersecting the second fin active pattern, is filled with a second source/drain region, and has a second depth in the third direction. A third recess which is formed in the substrate between the second and third gate electrodes intersecting the second fin active pattern, is filled with a third source/drain region, and has a third depth in the third direction. The third depth is greater than the first and second depths.

公开(公告)号：US20230253449A1

公开(公告)日：2023-08-10

申请号：US17935528

申请日：2022-09-26

申请人： Samsung Electronics Co., Ltd.

发明人： Dong Suk Shin ,  Hyun-Kwan Yu ,  Seok Hoon Kim ,  Pan Kwi Park ,  Yong Seung Kim ,  Jung Taek Kim

IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/762

CPC分类号： H01L29/0653 ,  H01L21/76224 ,  H01L29/4232 ,  H01L29/66553

摘要： A semiconductor device includes a lower pattern extending in a first direction and sheet patterns spaced apart therefrom in a second direction, a gate structure on the lower pattern and including a gate insulating layer, a gate spacer, and a gate electrode, a source/drain pattern on the lower pattern and in contact with the sheet patterns and the gate insulating layer, and a first etch blocking pattern between the gate spacer and the source/drain pattern. The gate spacer includes an inner sidewall extending in the third direction, and a connection sidewall extending from the inner sidewall in the first direction. The source/drain pattern includes a semiconductor filling layer on a semiconductor liner layer that is in contact with the sheet pattern and includes a facet surface extending from the connection sidewall. The first etch blocking pattern is in contact with the facet surface and the connection sidewall.

公开(公告)号：US20230116342A1

公开(公告)日：2023-04-13

申请号：US17829781

申请日：2022-06-01

申请人： Samsung Electronics Co., Ltd.

发明人： Won Hee Choi ,  Sung Uk Jang ,  Dong Suk Shin ,  Bong Jin Kuh ,  Kong Soo Lee

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/786 ,  H01L29/423 ,  H01L27/108

摘要： A semiconductor device is provided. A semiconductor device includes: a first active pattern spaced apart from a substrate and extending in a first direction; a second active pattern spaced apart further from the substrate than the first active pattern and extending in the first direction; a gate structure on the substrate, the gate structure extending in a second direction crossing the first direction and penetrating the first active pattern and the second active pattern; a first source/drain region on at least one side surface of the gate structure and connected to the first active pattern; a second source/drain region on at least one side surface of the gate structure and connected to the second active pattern; and a buffer layer between the substrate and the first active pattern, the buffer layer containing germanium.

公开(公告)号：US20230011153A1

公开(公告)日：2023-01-12

申请号：US17672233

申请日：2022-02-15

申请人： Samsung Electronics Co., Ltd.

发明人： Dong Woo Kim ,  Gyeom Kim ,  Jin Bum Kim ,  Dong Suk Shin ,  Sang Moon Lee

IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/417

摘要： A semiconductor device comprises an active pattern on a substrate; a plurality of nanosheets spaced apart from each other; a gate electrode surrounding each of the nanosheets; a field insulating layer surrounding side walls of the active pattern; an interlayer insulating layer on the field insulating layer; a source/drain region comprising a first doping layer on the active pattern, a second doping layer on the first doping layer, and a capping layer forming side walls adjacent to the interlayer insulating layer; a source/drain contact electrically connected to, and on, the source/drain region, and a silicide layer between the source/drain region and the source/drain contact which contacts contact with the second doping layer and extends to an upper surface of the source/drain region. The capping layer extends from an upper surface of the field insulating layer to the upper surface of the source/drain region along side walls of the silicide layer.

公开(公告)号：US10892263B2

公开(公告)日：2021-01-12

申请号：US16270865

申请日：2019-02-08

申请人： Samsung Electronics Co., Ltd.

发明人： Hoi Sung Chung ,  Tae Sung Kang ,  Dong Suk Shin ,  Kong Soo Lee ,  Jun-Won Lee

IPC分类号： H01L21/336 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78 ,  H01L27/108 ,  H01L21/265 ,  H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L29/51 ,  H01L21/311 ,  H01L21/324 ,  H01L29/08 ,  H01L29/40 ,  H01L21/266 ,  H01L29/04

摘要： Methods of fabricating a semiconductor device are provided. The methods may include forming a gate structure on a core-peri region of a substrate. The substrate may further include a cell region. The methods may also include forming a gate spacer on a sidewall of the gate structure, forming a first impurity region adjacent the gate spacer in the core-peri region of the substrate by performing a first ion implantation process, removing the gate spacer, forming a second impurity region in the core-peri region of the substrate between the gate structure and the first impurity region by performing a second ion implantation process, forming a stress film on the gate structure, an upper surface of the first impurity region, and an upper surface of the second impurity region, and forming a recrystallization region by crystallizing the first impurity region and the second impurity region by performing an annealing process.

公开(公告)号：US10790133B2

公开(公告)日：2020-09-29

申请号：US15416408

申请日：2017-01-26

申请人： Samsung Electronics Co., Ltd.

发明人： Keum Seok Park ,  Sun Jung Kim ,  Yi Hwan Kim ,  Pan Kwi Park ,  Dong Suk Shin ,  Hyun Kwan Yu ,  Seung Hun Lee

IPC分类号： B08B7/00 ,  B08B7/04 ,  H01L21/02 ,  H01L21/67 ,  H01L21/687 ,  H01L29/66 ,  H01J37/32 ,  H01L21/683 ,  H01L29/78 ,  H01L29/165

摘要： A precleaning apparatus includes a chamber having an internal space in which a substrate is cleaned, a substrate support disposed in the chamber and configured to support the substrate, a plasma generation unit disposed in the chamber and configured to generate plasma gas, a heating unit configured to heat the substrate on the substrate support, a cleaning gas supply unit configured to supply gas for oxide etching to the internal space of the chamber, and a hydrogen gas supply unit configured to supply hydrogen gas to the internal space of the chamber.

公开(公告)号：US10211322B1

公开(公告)日：2019-02-19

申请号：US15896277

申请日：2018-02-14

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jin Bum Kim ,  Tae Jin Park ,  Jong Min Lee ,  Seok Hoon Kim ,  Dong Chan Suh ,  Jeong Ho Yoo ,  Ha Kyu Seong ,  Dong Suk Shin

IPC分类号： H01L29/66 ,  H01L29/40 ,  H01L29/78

摘要： A semiconductor device and a method of manufacturing a semiconductor device, the semiconductor device including a channel pattern on a substrate, the channel pattern extending in a first direction; a gate pattern on the substrate, the gate pattern extending in a second direction crossing the first direction and surrounding the channel pattern; and an interface layer between the channel pattern and the gate pattern, the interface layer being formed on at least one surface of an upper surface and a lower surface of the channel pattern.