公开(公告)号：US20160350179A1

公开(公告)日：2016-12-01

申请号：US14818323

申请日：2015-08-05

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Tien-Ching Wang ,  Kuo-Hsin Lai

IPC: G06F11/10 ,  G11C16/26 ,  G11C16/08 ,  H03M13/45 ,  G11C29/52

Abstract: A decoding method, a memory storage device and a memory control circuit unit are provided. The method includes: reading a plurality of first memory cells according to a first soft-decision read voltage level to obtain a first soft-decision coding unit belonging to a block code; performing a first soft-decision decoding procedure for the first soft-decision coding unit; if the first soft-decision decoding procedure fails, reading the first memory cells according to a second soft-decision read voltage level to obtain a second soft-decision coding unit belonging to the block code, where a difference value between the first soft-decision read voltage level and the second soft-decision read voltage level is related to a wear degree of the first memory cells; and performing a second soft-decision decoding procedure for the second soft-decision coding unit. Accordingly, a decoding efficiency of block codes may be improved.

Abstract translation: 提供了解码方法，存储器存储装置和存储器控制电路单元。 该方法包括：根据第一软判决读取电压电平读取多个第一存储器单元以获得属于块码的第一软判决编码单元; 对所述第一软判决编码单元执行第一软判决解码过程; 如果第一软判决解码过程失败，则根据第二软判决读取电压电平读取第一存储器单元以获得属于块代码的第二软判决编码单元，其中第一软判决解码程序 读取电压电平，第二软判决读取电压电平与第一存储器单元的磨损程度相关; 以及对所述第二软判决编码单元执行第二软判决解码过程。 因此，可以提高块码的解码效率。

公开(公告)号：US20160306693A1

公开(公告)日：2016-10-20

申请号：US14745472

申请日：2015-06-22

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Tien-Ching Wang ,  Kuo-Hsin Lai

IPC: G06F11/10 ,  G11C29/50

CPC classification number: G06F11/1048 ,  G11C29/021 ,  G11C29/028 ,  G11C29/44 ,  G11C2029/5004

Abstract: A read voltage level estimating method, a memory storage device and a memory control circuit unit are provided. The method includes: reading a first region of a rewritable non-volatile memory module according to a first read voltage level to obtain a first encoding unit which belongs to a block code; performing a first decoding procedure on the first encoding unit and recording first decoding information; reading the first region according to a second read voltage level to obtain a second encoding unit which belongs to the block code; performing a second decoding procedure on the second encoding unit and recording second decoding information; and estimating and obtaining a third read voltage level according to the first decoding information and the second decoding information. Accordingly, a management ability of the rewritable non-volatile memory module adopting the block code may be improved.

Abstract translation: 提供读取电压电平估计方法，存储器存储装置和存储器控制电路单元。 该方法包括：根据第一读取电压电平读取可重写非易失性存储器模块的第一区域，以获得属于块码的第一编码单元; 对所述第一编码单元执行第一解码过程并记录第一解码信息; 根据第二读取电压电平读取第一区域以获得属于块码的第二编码单元; 对所述第二编码单元执行第二解码过程并记录第二解码信息; 以及根据第一解码信息和第二解码信息估计并获得第三读取电压电平。 因此，可以提高采用块代码的可重写非易失性存储器模块的管理能力。

公开(公告)号：US10025660B2

公开(公告)日：2018-07-17

申请号：US15009771

申请日：2016-01-28

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Tien-Ching Wang ,  Kuo-Hsin Lai

IPC: G06F11/00 ,  G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1012 ,  G11C29/52

Abstract: A data reading method for a rewritable non-volatile memory module is provided. The method includes performing an error correction decoding operation on an user data stream according to an error checking and correcting (ECC) code to generate a first decoded data stream; searching uncorrectable sub-data units from decoded sub-data units of the first decoded data stream; selecting a target sub-data unit from the uncorrectable sub-data units; adjusting the target sub-data unit in the first decoded data stream to generate an adjusted user data stream; and re-performing the error correction decoding operation on the adjusted user data stream to generate a second decoded data stream; if the second decoded data stream has no error bit, transmitting the second decoded data stream as a corrected data stream to a host system.

公开(公告)号：US20170168893A1

公开(公告)日：2017-06-15

申请号：US15009771

申请日：2016-01-28

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Tien-Ching Wang ,  Kuo-Hsin Lai

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1012 ,  G11C29/52

Abstract: A data reading method for a rewritable non-volatile memory module is provided. The method includes performing an error correction decoding operation on an user data stream according to an error checking and correcting (ECC) code to generate a first decoded data stream; searching uncorrectable sub-data units from decoded sub-data units of the first decoded data stream; selecting a target sub-data unit from the uncorrectable sub-data units; adjusting the target sub-data unit in the first decoded data stream to generate an adjusted user data stream; and re-performing the error correction decoding operation on the adjusted user data stream to generate a second decoded data stream; if the second decoded data stream has no error bit, transmitting the second decoded data stream as a corrected data stream to a host system.

公开(公告)号：US20160284414A1

公开(公告)日：2016-09-29

申请号：US14727878

申请日：2015-06-02

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Tien-Ching Wang ,  Kuo-Hsin Lai ,  Yu-Cheng Hsu ,  Chi-Heng Yang

IPC: G11C16/14 ,  G11C29/44 ,  G11C16/26 ,  G06F3/06 ,  G06F12/08

CPC classification number: G11C16/14 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0629 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/0802 ,  G06F2212/1044 ,  G06F2212/7203 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028 ,  G11C29/4401 ,  G11C2029/0409 ,  G11C2211/5648

Abstract: A data programming method, a memory storage device and a memory control circuit unit are provided. The method includes: receiving first data and programming the first data into a first lower physical programming unit; receiving second data; in response to the second data to be programmed into a first upper physical programming unit corresponding to the first lower physical programming unit, performing a first data obtaining operation which does not include reading the first lower physical programming unit by using a default read voltage; and programming the second data into the first upper physical programming unit according to the third data obtained through the first data obtaining operation.

Abstract translation: 提供数据编程方法，存储器存储装置和存储器控制电路单元。 该方法包括：接收第一数据并将第一数据编程到第一较低物理编程单元中; 接收第二数据; 响应于要被编程到与第一下部物理编程单元相对应的第一上部物理编程单元的第二数据，执行不包括通过使用默认读取电压读取第一下部物理编程单元的第一数据获取操作; 以及根据通过第一数据获取操作获得的第三数据将第二数据编程到第一上层物理编程单元中。

公开(公告)号：US20140293696A1

公开(公告)日：2014-10-02

申请号：US13901571

申请日：2013-05-24

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Tien-Ching Wang ,  Kuo-Hsin Lai ,  Yu-Cheng Hsu ,  Kuo-Yi Cheng

IPC: G11C16/26

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/3436 ,  G11C16/349

Abstract: A data reading method for a rewritable non-volatile memory module is provided. The method includes applying a test voltage to a word line of the rewritable non-volatile memory module to read a plurality of verification bit data. The method also includes calculating a variation of bit data identified as a first status among the verification bit data, obtaining a new read voltage value set based on the variation, and updating a threshold voltage set for the word line with the new read voltage value set. The method further includes using the updated threshold voltage set to read data from a physical page formed by memory cells connected to the word line. Accordingly, storage states of memory cells in the rewritable non-volatile memory module can be identified correctly, thereby preventing data stored in the memory cells from losing.

Abstract translation: 提供了一种可重写非易失性存储器模块的数据读取方法。 该方法包括将测试电压施加到可重写非易失性存储器模块的字线以读取多个验证位数据。 该方法还包括计算在验证位数据中识别为第一状态的位数据的变化，获得基于该变化设置的新的读取电压值，并且用新的读取电压值集更新用于字线的阈值电压 。 该方法还包括使用更新的阈值电压来从连接到字线的存储器单元形成的物理页读取数据。 因此，可以正确地识别可重写非易失性存储器模块中的存储单元的存储状态，从而防止存储在存储单元中的数据丢失。

公开(公告)号：US20190252035A1

公开(公告)日：2019-08-15

申请号：US16393982

申请日：2019-04-25

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Tien-Ching Wang ,  Kuo-Hsin Lai

IPC: G11C29/52 ,  G06F11/10 ,  G11C29/02 ,  H03M13/29 ,  G11C29/42

CPC classification number: G11C29/52 ,  G06F11/1012 ,  G11C11/5642 ,  G11C16/26 ,  G11C29/021 ,  G11C29/028 ,  G11C29/42 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/2909 ,  H03M13/2963

Abstract: A decoding method, a memory storage device and a memory control circuit unit are provided. The method includes: arranging a plurality of first voltage levels which are used continuously for reading first data from a plurality of first memory cells according to a first wear degree of the first memory cells; decoding the first data which is read by the arranged first voltage levels; arranging a plurality of second voltage levels which are used continuously for reading second data from the first memory cells according to a second wear degree of the first memory cells, wherein the first wear degree of the first memory cells is different from the second wear degree of the first memory cells, and a voltage gap between any two neighboring voltages levels among the first voltage levels is different from a voltage gap between any two neighboring voltage levels among the second voltage levels; and decoding the second data which is read by the arranged second voltage levels.

公开(公告)号：US09582224B2

公开(公告)日：2017-02-28

申请号：US14702768

申请日：2015-05-04

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Kuo-Hsin Lai ,  Tien-Ching Wang

IPC: G06F12/00 ,  G06F3/06 ,  G11C16/34

CPC classification number: G06F3/0688 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G11C16/34

Abstract: A memory control circuit unit including a plurality of data randomizer circuits and a data selection circuit is provided. When a first data stream is received from a host system, the first data stream is input into the data randomizer circuits to respectively output a plurality of second data streams. The data selection circuit selects one of the second data streams as a third data stream according to contents of the second data streams, and the third data stream is programmed into a rewritable non-volatile memory module. Accordingly, data written into the rewritable non-volatile memory module can be effectively disarranged.

Abstract translation: 提供包括多个数据随机化器电路和数据选择电路的存储器控​​制电路单元。 当从主机系统接收到第一数据流时，将第一数据流输入到数据随机化器电路中，以分别输出多个第二数据流。 数据选择电路根据第二数据流的内容选择第二数据流中的一个作为第三数据流，并将第三数据流编程到可重写的非易失性存储器模块中。 因此，写入可重写非易失性存储器模块的数据可以被有效地排除。

公开(公告)号：US09529666B2

公开(公告)日：2016-12-27

申请号：US14295355

申请日：2014-06-04

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Shao-Wei Yen ,  Yu-Hsiang Lin ,  Tien-Ching Wang ,  Kuo-Hsin Lai ,  Siu-Tung Lam

IPC: G11C29/00 ,  G06F11/10 ,  G11C29/42 ,  H03M13/37 ,  H03M13/00 ,  H03M13/11 ,  H03M13/15 ,  H03M13/23

CPC classification number: G06F11/1008 ,  G06F11/1012 ,  G11C29/42 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/152 ,  H03M13/23 ,  H03M13/3715 ,  H03M13/3723 ,  H03M13/6325

Abstract: A decoding method, a memory storage device and a memory controlling circuit are provided. The decoding method includes: sending a read command sequence configured to read the memory cells, so as to obtain a plurality of first verification bits; executing a first decoding procedure according to the first verification bits, and determining whether a first valid codeword is generated; if the first valid codeword is not generated, sending another read command sequence configured to obtain a plurality of second verification bits; calculating a total number of the memory cells conforming to a specific condition according to the second verification bits; obtaining a channel reliability message according to the total number; and executing a second decoding procedure according to the channel reliability message. Accordingly, a correcting ability of decoding may be improved.

Abstract translation: 提供了解码方法，存储器存储装置和存储器控制电路。 解码方法包括：发送配置为读取存储单元的读命令序列，以获得多个第一验证位; 执行根据所述第一验证比特的第一解码过程，以及确定是否生成第一有效码字; 如果不产生第一有效码字，则发送另一读取命令序列，被配置为获得多个第二验证比特; 根据第二验证位计算符合特定条件的存储单元的总数; 根据总数获取信道可靠性消息; 以及根据信道可靠性消息执行第二解码过程。 因此，可以提高解码的校正能力。

公开(公告)号：US20160247575A1

公开(公告)日：2016-08-25

申请号：US14682123

申请日：2015-04-09

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Tien-Ching Wang ,  Kuo-Hsin Lai

IPC: G11C16/26 ,  G11C29/52 ,  G06F11/10 ,  G11C16/08 ,  G11C16/04

CPC classification number: G11C16/26 ,  G06F11/1048 ,  G11C7/1006 ,  G11C2029/0411

Abstract: A data reading method is provided. The data reading method includes receiving a read command from a host system; sending a first read command sequence to obtain a first data string from memory cells of a rewritable non-volatile memory module; performing a decoding procedure on the first data string to generate a decoded first data string; and, if there is an error bit in the decoded first data string, sending a second read command sequence to obtain a second data string from the memory cells, performing a logical operation on the decoded first data string and the second data string to obtain an adjusting data string, adjusting the decoded first data string according to the adjusting data string to obtain an adjusted first data string, and using a data string obtained after re-performing the decoding procedure on the adjusted first data string as the decoded first data string.

Abstract translation: 提供了一种数据读取方法。 数据读取方法包括从主机系统接收读取命令; 发送第一读取命令序列以从可重写非易失性存储器模块的存储器单元获得第一数据串; 对所述第一数据串执行解码过程以生成解码的第一数据串; 并且如果在解码的第一数据串中存在错误位，则从存储器单元发送第二读取命令序列以获得第二数据串，对解码的第一数据串和第二数据串执行逻辑运算以获得 调整数据串，根据调整数据串调整解码后的第一数据串，得到经调整后的第一数据串，并使用对经过调整的第一数据串进行解码过程后获得的数据串作为解码后的第一数据串。