Invention Grant
US09529666B2 Decoding method, memory storage device and memory controlling circuit unit
有权
解码方法,存储器存储装置和存储器控制电路单元
- Patent Title: Decoding method, memory storage device and memory controlling circuit unit
- Patent Title (中): 解码方法,存储器存储装置和存储器控制电路单元
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Application No.: US14295355Application Date: 2014-06-04
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Publication No.: US09529666B2Publication Date: 2016-12-27
- Inventor: Wei Lin , Shao-Wei Yen , Yu-Hsiang Lin , Tien-Ching Wang , Kuo-Hsin Lai , Siu-Tung Lam
- Applicant: PHISON ELECTRONICS CORP.
- Applicant Address: TW Miaoli
- Assignee: PHISON ELECTRONICS CORP.
- Current Assignee: PHISON ELECTRONICS CORP.
- Current Assignee Address: TW Miaoli
- Agency: Jianq Chyun IP Office
- Priority: TW103113697A 20140415
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G06F11/10 ; G11C29/42 ; H03M13/37 ; H03M13/00 ; H03M13/11 ; H03M13/15 ; H03M13/23

Abstract:
A decoding method, a memory storage device and a memory controlling circuit are provided. The decoding method includes: sending a read command sequence configured to read the memory cells, so as to obtain a plurality of first verification bits; executing a first decoding procedure according to the first verification bits, and determining whether a first valid codeword is generated; if the first valid codeword is not generated, sending another read command sequence configured to obtain a plurality of second verification bits; calculating a total number of the memory cells conforming to a specific condition according to the second verification bits; obtaining a channel reliability message according to the total number; and executing a second decoding procedure according to the channel reliability message. Accordingly, a correcting ability of decoding may be improved.
Public/Granted literature
- US20150293811A1 DECODING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROLLING CIRCUIT UNIT Public/Granted day:2015-10-15
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