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公开(公告)号：US20190163567A1
公开(公告)日：2019-05-30
申请号：US15884407
申请日：2018-01-31
Applicant: PHISON ELECTRONICS CORP.
Inventor： Yu-Hsiang Lin , Shao-Wei Yen , Cheng-Che Yang , Kuo-Hsin Lai
Abstract: A decoding method for a memory storage device including a rewritable non-volatile memory module is provided according to an exemplary embodiment of the invention. The method includes: reading at least one memory cells by using at least one read voltage level to obtain a codeword; performing a parity check operation on the codeword by an error checking and correcting circuit to generate a syndrome sum corresponding to the codeword; and dynamically adjusting a first parameter used by the error checking and correcting circuit in a first decoding operation based on whether the syndrome sum is less than a first threshold value and performing the first decoding operation on the codeword by the error checking and correcting circuit by using the first parameter.
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公开(公告)号：US10191806B2
公开(公告)日：2019-01-29
申请号：US15299469
申请日：2016-10-21
Applicant: PHISON ELECTRONICS CORP.
Inventor： Yu-Hsiang Lin , Shao-Wei Yen , Cheng-Che Yang , Kuo-Hsin Lai
Abstract: In one exemplary embodiment, the decoding method includes: reading first data from a plurality of first memory cells of a rewritable non-volatile memory module; performing a first decoding operation on the first data based on a first decoding condition; and performing a second decoding operation on the first data based on a second decoding condition if the first decoding operation conforms to a first default status, where a strict level of locating an error bit in the first data based on the second decoding condition is higher than a strict level of locating the error bit in the first data based on the first decoding condition. Therefore, a decoding efficiency of a memory storage device can be improved.
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公开(公告)号：US20180293131A1
公开(公告)日：2018-10-11
申请号：US15604661
申请日：2017-05-25
Applicant: PHISON ELECTRONICS CORP.
Inventor： Yu-Hsiang Lin , Shao-Wei Yen , Cheng-Che Yang , Kuo-Hsin Lai
CPC classification number: G06F11/1068 , G06F3/0619 , G06F3/0659 , G06F3/0679 , G11C29/52
Abstract: A decoding method, a memory storage device and a memory control circuit unit. The method includes: reading a plurality of bits from a plurality of first memory cells; performing a first decoding operation on the bits according to first reliability information; and performing a second decoding operation on the bits according to second reliability information if the first decoding operation fails and meets a default condition, and the second reliability information is different from the first reliability information, and a correction ability of the second reliability information for a first type error of the bits is higher than a correction ability of the first reliability information for the first type error. In addition, the first type error is generated by performing a specific programming operation on the first memory cells based on error data.
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公开(公告)号：US20180046542A1
公开(公告)日：2018-02-15
申请号：US15299469
申请日：2016-10-21
Applicant: PHISON ELECTRONICS CORP.
Inventor： Yu-Hsiang Lin , Shao-Wei Yen , Cheng-Che Yang , Kuo-Hsin Lai
CPC classification number: G06F11/1068 , G06F3/0611 , G06F3/0619 , G06F3/064 , G06F3/0659 , G06F3/0679 , G06F3/0688 , G06F11/1012 , G11C29/52 , H03M13/1108 , H03M13/1575 , H03M13/3715
Abstract: In one exemplary embodiment, the decoding method includes: reading first data from a plurality of first memory cells of a rewritable non-volatile memory module; performing a first decoding operation on the first data based on a first decoding condition; and performing a second decoding operation on the first data based on a second decoding condition if the first decoding operation conforms to a first default status, where a strict level of locating an error bit in the first data based on the second decoding condition is higher than a strict level of locating the error bit in the first data based on the first decoding condition. Therefore, a decoding efficiency of a memory storage device can be improved.
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5.发明授权Decoding method, memory storage device and memory controlling circuit unit 有权解码方法，存储器存储装置和存储器控制电路单元公开(公告)号：US09529666B2
公开(公告)日：2016-12-27
申请号：US14295355
申请日：2014-06-04
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei Lin , Shao-Wei Yen , Yu-Hsiang Lin , Tien-Ching Wang , Kuo-Hsin Lai , Siu-Tung Lam
CPC classification number: G06F11/1008 , G06F11/1012 , G11C29/42 , H03M13/1108 , H03M13/1111 , H03M13/152 , H03M13/23 , H03M13/3715 , H03M13/3723 , H03M13/6325
Abstract: A decoding method, a memory storage device and a memory controlling circuit are provided. The decoding method includes: sending a read command sequence configured to read the memory cells, so as to obtain a plurality of first verification bits; executing a first decoding procedure according to the first verification bits, and determining whether a first valid codeword is generated; if the first valid codeword is not generated, sending another read command sequence configured to obtain a plurality of second verification bits; calculating a total number of the memory cells conforming to a specific condition according to the second verification bits; obtaining a channel reliability message according to the total number; and executing a second decoding procedure according to the channel reliability message. Accordingly, a correcting ability of decoding may be improved.
Abstract translation: 提供了解码方法，存储器存储装置和存储器控制电路。 解码方法包括：发送配置为读取存储单元的读命令序列，以获得多个第一验证位; 执行根据所述第一验证比特的第一解码过程，以及确定是否生成第一有效码字; 如果不产生第一有效码字，则发送另一读取命令序列，被配置为获得多个第二验证比特; 根据第二验证位计算符合特定条件的存储单元的总数; 根据总数获取信道可靠性消息; 以及根据信道可靠性消息执行第二解码过程。 因此，可以提高解码的校正能力。
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Patent Agency Ranking
6.发明申请公开(公告)号：US20150095741A1
公开(公告)日：2015-04-02
申请号：US14109959
申请日：2013-12-18
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei Lin , Shao-Wei Yen , Yu-Hsiang Lin , Kuo-Hsin Lai , Kuo-Yi Cheng
IPC: G06F11/10
CPC classification number: G06F11/1008 , G06F11/1048
Abstract: A decoding method, a memory storage device and a memory controlling circuit unit are provided. The method includes: reading memory cells according to a first reading voltage to obtain first verifying bits; executing a decoding procedure including a probability decoding algorithm according to the first verifying bits to obtain first decoded bits, and determining whether a decoding is successful by using the decoded bits; if the decoding is failed, reading the memory cells according to a second reading voltage to obtain second verifying bits, and executing the decoding procedure according to the second verifying bits to obtain second decoded bits. The second reading voltage is different from the first reading voltage, and the number of the second reading voltage is equal to the number of the first reading voltage. Accordingly, the ability for correcting errors is improved.
Abstract translation: 提供了解码方法，存储器存储装置和存储器控制电路单元。 该方法包括：根据第一读取电压读取存储器单元以获得第一验证位; 执行包括根据第一验证位的概率解码算法的解码过程以获得第一解码比特，并且通过使用解码比特来确定解码是否成功; 如果解码失败，则根据第二读取电压读取存储器单元以获得第二验证位，并且根据第二验证位执行解码过程以获得第二解码位。 第二读取电压与第一读取电压不同，第二读取电压的数量等于第一读取电压的数量。 因此，能够提高校正误差的能力。
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公开(公告)号：US11146295B1
公开(公告)日：2021-10-12
申请号：US16862576
申请日：2020-04-30
Applicant: PHISON ELECTRONICS CORP.
Inventor： Yu-Hsiang Lin
Abstract: A decoding method, a memory storage device and a memory controlling circuit unit are provided. The method includes: receiving a read command sequence for reading a plurality of bits from the memory cells; calculating a first count value of a first value and a second count value of a second value in the bits; and adjusting a decoding parameter corresponding to the bits to a specific decoding parameter according to the first count value and the second count value, and performing a decoding operation according to the specific decoding parameter, where the adjusted decoding parameter affects a probability that the bits are considered as an error bit in the decoding operation.
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公开(公告)号：US20210306010A1
公开(公告)日：2021-09-30
申请号：US16862576
申请日：2020-04-30
Applicant: PHISON ELECTRONICS CORP.
Inventor： Yu-Hsiang Lin
Abstract: A decoding method, a memory storage device and a memory controlling circuit unit are provided. The method includes: receiving a read command sequence for reading a plurality of bits from the memory cells; calculating a first count value of a first value and a second count value of a second value in the bits; and adjusting a decoding parameter corresponding to the bits to a specific decoding parameter according to the first count value and the second count value, and performing a decoding operation according to the specific decoding parameter, where the adjusted decoding parameter affects a probability that the bits are considered as an error bit in the decoding operation.
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公开(公告)号：US10324787B2
公开(公告)日：2019-06-18
申请号：US15831405
申请日：2017-12-05
Applicant: PHISON ELECTRONICS CORP.
Inventor： Yu-Hsiang Lin , Shao-Wei Yen , Yu-Siang Yang , Kuo-Hsin Lai
Abstract: A decoding method is provided according to an exemplary embodiment of the invention. The decoding method includes: reading a data set from at least two physical units of a rewritable non-volatile memory module by using at least one read voltage level; performing a first-type decoding operation for first data by using the data set and recording decoding information of the first-type decoding operation if the data set conforms to a default condition; adjusting reliability information corresponding to the first data according to the recorded decoding information, and the reliability information is not used in the first-type decoding operation, and the adjusted reliability information is different from default reliability information corresponding to the first data; and performing a second-type decoding operation for the first data according to the adjusted reliability information.
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公开(公告)号：US20170294217A1
公开(公告)日：2017-10-12
申请号：US15170931
申请日：2016-06-01
Applicant: PHISON ELECTRONICS CORP.
Inventor： Yu-Hsiang Lin , Shao-Wei Yen , Cheng-Che Yang , Kuo-Hsin Lai
CPC classification number: G11C7/00 , G06F11/1012 , G06F11/1068 , G11C29/52 , G11C2029/0409 , G11C2029/0411
Abstract: A decoding method, a memory storage device and a memory control circuit unit are provided. The method includes: reading data from a plurality of first memory cells of a rewritable non-volatile memory module; estimating an error bit occurrence rate of the data before performing a first decoding process on the data; and performing the first decoding process on the data by using a first decoding parameter according to the estimated error bit occurrence rate, wherein the first decoding parameter corresponds to a strict level for locating an error bit in the first decoding process. As a result, a decoding efficiency of the memory storage device can be improved.
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