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公开(公告)号：US20170302299A1
公开(公告)日：2017-10-19
申请号：US15188995
申请日：2016-06-22
Applicant: PHISON ELECTRONICS CORP.
Inventor： Yu-Hsiang Lin , Cheng-Che Yang , Shao-Wei Yen , Kuo-Hsin Lai
CPC classification number: H03M13/2906 , G06F11/1012 , G06F11/1068 , G11C29/52 , G11C29/702 , H03M13/1102 , H03M13/2927 , H03M13/3776
Abstract: A data processing method, a memory storage device and a memory control circuit unit are provided. The method includes: receiving first write data; performing a first stage encoding operation of a low-density parity-check (LDPC) code on the first write data and generating first transition data; performing a second stage encoding operation of the LDPC code on the first transition data and generating a first error correcting code (ECC); receiving second write data; and performing the first stage encoding operation of the LDPC code on the second write data during a time period of performing the second stage encoding operation of the LDPC code on the first transition data. Accordingly, the data processing efficiency corresponding to the LDPC code can be improved.
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2.发明授权公开(公告)号：US09583217B2
公开(公告)日：2017-02-28
申请号：US14296383
申请日：2014-06-04
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei Lin , Shao-Wei Yen , Yu-Hsiang Lin , Kuo-Hsin Lai
CPC classification number: G11C29/52 , G06F11/1012 , G11C2029/0411 , H03M13/05 , H03M13/3746
Abstract: A decoding method, a memory storage device and a memory control circuit unit are provided, the decoding method includes: reading a plurality of memory cells according to hard decision voltage to obtain hard bit; performing a parity check procedure for the hard bit to obtain a plurality of syndromes; determining whether the hard bit has error according to the syndromes; if the hard bit has the error, updating the hard bit according to channel information of the hard bit and syndrome weight information corresponding to the hard bit.
Abstract translation: 提供了解码方法，存储器存储装置和存储器控制电路单元，该解码方法包括：根据硬判定电压读取多个存储单元以获得硬比特; 对所述硬比特执行奇偶校验处理以获得多个综合征; 根据综合征确定硬比特是否有错误; 如果硬比特错误，则根据与硬比特相对应的硬比特和综合征权重信息的信道信息更新硬比特。
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3.发明申请DECODING METHOD, MEMORY STORAGE DEVICE, AND MEMORY CONTROLLING CIRCUIT UNIT 有权解码方法，存储器存储设备和存储器控制电路单元公开(公告)号：US20150186212A1
公开(公告)日：2015-07-02
申请号：US14190103
申请日：2014-02-26
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei Lin , Shao-Wei Yen , Yu-Hsiang Lin , Kuo-Hsin Lai
IPC: G06F11/10
CPC classification number: G06F11/1076 , G06F11/1012 , G06F11/1068 , G06F11/1072 , G11C11/5642 , G11C2029/0411 , H03M13/1102 , H03M13/1108 , H03M13/1111 , H03M13/3707
Abstract: A decoding method, a memory storage device and a memory controlling circuit unit are provided. The decoding method includes: reading at least one memory cell according to a first read voltage to obtain at least one first verification bit; executing a hard bit mode decoding procedure according to the first verification bit, and determining whether a first valid codeword is generated by the hard bit mode decoding procedure; if the first valid codeword is not generated by the hard bit mode decoding procedure, obtaining storage information of the memory cell; deciding a voltage number according to the storage information; reading the memory cell according to second read voltages matching the voltage number to obtain second verification bits; and executing a soft bit mode decoding procedure according to the second verification bits. Accordingly, the speed of decoding is increased.
Abstract translation: 提供了解码方法，存储器存储装置和存储器控制电路单元。 解码方法包括：根据第一读取电压读取至少一个存储器单元以获得至少一个第一验证位; 执行根据第一验证位的硬比特模式解码过程，以及通过硬比特模式解码过程来确定是否产生第一有效码字; 如果第一有效码字不是由硬比特模式解码过程产生的，则获得存储单元的存储信息; 根据存储信息确定电压数; 根据与电压数相匹配的第二读取电压来读取存储器单元以获得第二验证位; 以及根据第二验证位执行软位模式解码过程。 因此，解码速度提高。
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公开(公告)号：US10324787B2
公开(公告)日：2019-06-18
申请号：US15831405
申请日：2017-12-05
Applicant: PHISON ELECTRONICS CORP.
Inventor： Yu-Hsiang Lin , Shao-Wei Yen , Yu-Siang Yang , Kuo-Hsin Lai
Abstract: A decoding method is provided according to an exemplary embodiment of the invention. The decoding method includes: reading a data set from at least two physical units of a rewritable non-volatile memory module by using at least one read voltage level; performing a first-type decoding operation for first data by using the data set and recording decoding information of the first-type decoding operation if the data set conforms to a default condition; adjusting reliability information corresponding to the first data according to the recorded decoding information, and the reliability information is not used in the first-type decoding operation, and the adjusted reliability information is different from default reliability information corresponding to the first data; and performing a second-type decoding operation for the first data according to the adjusted reliability information.
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公开(公告)号：US20170294217A1
公开(公告)日：2017-10-12
申请号：US15170931
申请日：2016-06-01
Applicant: PHISON ELECTRONICS CORP.
Inventor： Yu-Hsiang Lin , Shao-Wei Yen , Cheng-Che Yang , Kuo-Hsin Lai
CPC classification number: G11C7/00 , G06F11/1012 , G06F11/1068 , G11C29/52 , G11C2029/0409 , G11C2029/0411
Abstract: A decoding method, a memory storage device and a memory control circuit unit are provided. The method includes: reading data from a plurality of first memory cells of a rewritable non-volatile memory module; estimating an error bit occurrence rate of the data before performing a first decoding process on the data; and performing the first decoding process on the data by using a first decoding parameter according to the estimated error bit occurrence rate, wherein the first decoding parameter corresponds to a strict level for locating an error bit in the first decoding process. As a result, a decoding efficiency of the memory storage device can be improved.
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Patent Agency Ranking
6.发明授权Data reading method, and control circuit, memory module and memory storage apparatus using the same 有权数据读取方法和控制电路，存储器模块和使用其的存储器存储装置公开(公告)号：US08830750B1
公开(公告)日：2014-09-09
申请号：US13928356
申请日：2013-06-26
Applicant: Phison Electronics Corp.
Inventor： Kuo-Yi Cheng , Wei Lin , Yu-Hsiang Lin , Shao-Wei Yen , Kuo-Hsin Lai
CPC classification number: G11C16/26 , G11C11/5642 , G11C16/0483 , G11C2211/5621
Abstract: A data reading method for a rewritable non-volatile memory module is provided. The method includes determining a corresponding read voltage based on a critical voltage distribution of memory cells of a word line. The method further includes: if the critical voltage distribution of the memory cells is a right-offset distribution, applying a set of right adjustment read voltage to the word line to read a plurality of bit data as corresponding soft values; and decoding the corresponding soft values to obtain page data stored in the memory cells. Herein, the set of right adjustment read voltage includes a plurality of positive adjustment read voltages and a plurality of negative adjustment read voltages and the number of the positive adjustment read voltages is more than the number of the negative adjustment read voltages. Accordingly, storage states of the memory cells can be identified correctly.
Abstract translation: 提供了一种可重写非易失性存储器模块的数据读取方法。 该方法包括基于字线的存储器单元的临界电压分布来确定相应的读取电压。 该方法还包括：如果存储器单元的临界电压分布是右偏移分布，则将一组正确的调整读取电压施加到字线以读取多个位数据作为相应的软值; 并解码对应的软值以获得存储在存储单元中的页面数据。 这里，正确调整读取电压的集合包括多个正调整读取电压和多个负调整读取电压，并且正调整读取电压的数量大于负调整读取电压的数量。 因此，可以正确地识别存储器单元的存储状态。
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公开(公告)号：US20190163567A1
公开(公告)日：2019-05-30
申请号：US15884407
申请日：2018-01-31
Applicant: PHISON ELECTRONICS CORP.
Inventor： Yu-Hsiang Lin , Shao-Wei Yen , Cheng-Che Yang , Kuo-Hsin Lai
Abstract: A decoding method for a memory storage device including a rewritable non-volatile memory module is provided according to an exemplary embodiment of the invention. The method includes: reading at least one memory cells by using at least one read voltage level to obtain a codeword; performing a parity check operation on the codeword by an error checking and correcting circuit to generate a syndrome sum corresponding to the codeword; and dynamically adjusting a first parameter used by the error checking and correcting circuit in a first decoding operation based on whether the syndrome sum is less than a first threshold value and performing the first decoding operation on the codeword by the error checking and correcting circuit by using the first parameter.
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公开(公告)号：US10191806B2
公开(公告)日：2019-01-29
申请号：US15299469
申请日：2016-10-21
Applicant: PHISON ELECTRONICS CORP.
Inventor： Yu-Hsiang Lin , Shao-Wei Yen , Cheng-Che Yang , Kuo-Hsin Lai
Abstract: In one exemplary embodiment, the decoding method includes: reading first data from a plurality of first memory cells of a rewritable non-volatile memory module; performing a first decoding operation on the first data based on a first decoding condition; and performing a second decoding operation on the first data based on a second decoding condition if the first decoding operation conforms to a first default status, where a strict level of locating an error bit in the first data based on the second decoding condition is higher than a strict level of locating the error bit in the first data based on the first decoding condition. Therefore, a decoding efficiency of a memory storage device can be improved.
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公开(公告)号：US20180293131A1
公开(公告)日：2018-10-11
申请号：US15604661
申请日：2017-05-25
Applicant: PHISON ELECTRONICS CORP.
Inventor： Yu-Hsiang Lin , Shao-Wei Yen , Cheng-Che Yang , Kuo-Hsin Lai
CPC classification number: G06F11/1068 , G06F3/0619 , G06F3/0659 , G06F3/0679 , G11C29/52
Abstract: A decoding method, a memory storage device and a memory control circuit unit. The method includes: reading a plurality of bits from a plurality of first memory cells; performing a first decoding operation on the bits according to first reliability information; and performing a second decoding operation on the bits according to second reliability information if the first decoding operation fails and meets a default condition, and the second reliability information is different from the first reliability information, and a correction ability of the second reliability information for a first type error of the bits is higher than a correction ability of the first reliability information for the first type error. In addition, the first type error is generated by performing a specific programming operation on the first memory cells based on error data.
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公开(公告)号：US20180046542A1
公开(公告)日：2018-02-15
申请号：US15299469
申请日：2016-10-21
Applicant: PHISON ELECTRONICS CORP.
Inventor： Yu-Hsiang Lin , Shao-Wei Yen , Cheng-Che Yang , Kuo-Hsin Lai
CPC classification number: G06F11/1068 , G06F3/0611 , G06F3/0619 , G06F3/064 , G06F3/0659 , G06F3/0679 , G06F3/0688 , G06F11/1012 , G11C29/52 , H03M13/1108 , H03M13/1575 , H03M13/3715
Abstract: In one exemplary embodiment, the decoding method includes: reading first data from a plurality of first memory cells of a rewritable non-volatile memory module; performing a first decoding operation on the first data based on a first decoding condition; and performing a second decoding operation on the first data based on a second decoding condition if the first decoding operation conforms to a first default status, where a strict level of locating an error bit in the first data based on the second decoding condition is higher than a strict level of locating the error bit in the first data based on the first decoding condition. Therefore, a decoding efficiency of a memory storage device can be improved.
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