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公开(公告)号：US20170294217A1
公开(公告)日：2017-10-12
申请号：US15170931
申请日：2016-06-01
Applicant: PHISON ELECTRONICS CORP.
Inventor： Yu-Hsiang Lin , Shao-Wei Yen , Cheng-Che Yang , Kuo-Hsin Lai
CPC classification number: G11C7/00 , G06F11/1012 , G06F11/1068 , G11C29/52 , G11C2029/0409 , G11C2029/0411
Abstract: A decoding method, a memory storage device and a memory control circuit unit are provided. The method includes: reading data from a plurality of first memory cells of a rewritable non-volatile memory module; estimating an error bit occurrence rate of the data before performing a first decoding process on the data; and performing the first decoding process on the data by using a first decoding parameter according to the estimated error bit occurrence rate, wherein the first decoding parameter corresponds to a strict level for locating an error bit in the first decoding process. As a result, a decoding efficiency of the memory storage device can be improved.
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公开(公告)号：US11430538B1
公开(公告)日：2022-08-30
申请号：US17195547
申请日：2021-03-08
Applicant: PHISON ELECTRONICS CORP.
Inventor： Yu-Hsiang Lin , Pochiao Chou , Cheng-Che Yang
Abstract: A memory control method, a memory storage device, and a memory control circuit unit are provided. The method includes: executing a single page encoding operation on first data stored in a first type physical unit to generate local parity data; executing a global encoding operation on second data stored in at least two of the first type physical unit, a second type physical unit, and a third type physical unit to generate global parity data; reading the second data from the at least two of the first type physical unit, the second type physical unit, and the third type physical unit in response to a failure of a single page decoding operation for the first data; and executing a global decoding operation on the second data according to the global parity data.
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公开(公告)号：US20170302299A1
公开(公告)日：2017-10-19
申请号：US15188995
申请日：2016-06-22
Applicant: PHISON ELECTRONICS CORP.
Inventor： Yu-Hsiang Lin , Cheng-Che Yang , Shao-Wei Yen , Kuo-Hsin Lai
CPC classification number: H03M13/2906 , G06F11/1012 , G06F11/1068 , G11C29/52 , G11C29/702 , H03M13/1102 , H03M13/2927 , H03M13/3776
Abstract: A data processing method, a memory storage device and a memory control circuit unit are provided. The method includes: receiving first write data; performing a first stage encoding operation of a low-density parity-check (LDPC) code on the first write data and generating first transition data; performing a second stage encoding operation of the LDPC code on the first transition data and generating a first error correcting code (ECC); receiving second write data; and performing the first stage encoding operation of the LDPC code on the second write data during a time period of performing the second stage encoding operation of the LDPC code on the first transition data. Accordingly, the data processing efficiency corresponding to the LDPC code can be improved.
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公开(公告)号：US20190163567A1
公开(公告)日：2019-05-30
申请号：US15884407
申请日：2018-01-31
Applicant: PHISON ELECTRONICS CORP.
Inventor： Yu-Hsiang Lin , Shao-Wei Yen , Cheng-Che Yang , Kuo-Hsin Lai
Abstract: A decoding method for a memory storage device including a rewritable non-volatile memory module is provided according to an exemplary embodiment of the invention. The method includes: reading at least one memory cells by using at least one read voltage level to obtain a codeword; performing a parity check operation on the codeword by an error checking and correcting circuit to generate a syndrome sum corresponding to the codeword; and dynamically adjusting a first parameter used by the error checking and correcting circuit in a first decoding operation based on whether the syndrome sum is less than a first threshold value and performing the first decoding operation on the codeword by the error checking and correcting circuit by using the first parameter.
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公开(公告)号：US10191806B2
公开(公告)日：2019-01-29
申请号：US15299469
申请日：2016-10-21
Applicant: PHISON ELECTRONICS CORP.
Inventor： Yu-Hsiang Lin , Shao-Wei Yen , Cheng-Che Yang , Kuo-Hsin Lai
Abstract: In one exemplary embodiment, the decoding method includes: reading first data from a plurality of first memory cells of a rewritable non-volatile memory module; performing a first decoding operation on the first data based on a first decoding condition; and performing a second decoding operation on the first data based on a second decoding condition if the first decoding operation conforms to a first default status, where a strict level of locating an error bit in the first data based on the second decoding condition is higher than a strict level of locating the error bit in the first data based on the first decoding condition. Therefore, a decoding efficiency of a memory storage device can be improved.
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Patent Agency Ranking
公开(公告)号：US20180293131A1
公开(公告)日：2018-10-11
申请号：US15604661
申请日：2017-05-25
Applicant: PHISON ELECTRONICS CORP.
Inventor： Yu-Hsiang Lin , Shao-Wei Yen , Cheng-Che Yang , Kuo-Hsin Lai
CPC classification number: G06F11/1068 , G06F3/0619 , G06F3/0659 , G06F3/0679 , G11C29/52
Abstract: A decoding method, a memory storage device and a memory control circuit unit. The method includes: reading a plurality of bits from a plurality of first memory cells; performing a first decoding operation on the bits according to first reliability information; and performing a second decoding operation on the bits according to second reliability information if the first decoding operation fails and meets a default condition, and the second reliability information is different from the first reliability information, and a correction ability of the second reliability information for a first type error of the bits is higher than a correction ability of the first reliability information for the first type error. In addition, the first type error is generated by performing a specific programming operation on the first memory cells based on error data.
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公开(公告)号：US20180046542A1
公开(公告)日：2018-02-15
申请号：US15299469
申请日：2016-10-21
Applicant: PHISON ELECTRONICS CORP.
Inventor： Yu-Hsiang Lin , Shao-Wei Yen , Cheng-Che Yang , Kuo-Hsin Lai
CPC classification number: G06F11/1068 , G06F3/0611 , G06F3/0619 , G06F3/064 , G06F3/0659 , G06F3/0679 , G06F3/0688 , G06F11/1012 , G11C29/52 , H03M13/1108 , H03M13/1575 , H03M13/3715
Abstract: In one exemplary embodiment, the decoding method includes: reading first data from a plurality of first memory cells of a rewritable non-volatile memory module; performing a first decoding operation on the first data based on a first decoding condition; and performing a second decoding operation on the first data based on a second decoding condition if the first decoding operation conforms to a first default status, where a strict level of locating an error bit in the first data based on the second decoding condition is higher than a strict level of locating the error bit in the first data based on the first decoding condition. Therefore, a decoding efficiency of a memory storage device can be improved.
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公开(公告)号：US20220254431A1
公开(公告)日：2022-08-11
申请号：US17195547
申请日：2021-03-08
Applicant: PHISON ELECTRONICS CORP.
Inventor： Yu-Hsiang Lin , Pochiao Chou , Cheng-Che Yang
Abstract: A memory control method, a memory storage device, and a memory control circuit unit are provided. The method includes: executing a single page encoding operation on first data stored in a first type physical unit to generate local parity data; executing a global encoding operation on second data stored in at least two of the first type physical unit, a second type physical unit, and a third type physical unit to generate global parity data; reading the second data from the at least two of the first type physical unit, the second type physical unit, and the third type physical unit in response to a failure of a single page decoding operation for the first data; and executing a global decoding operation on the second data according to the global parity data.
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公开(公告)号：US10534665B2
公开(公告)日：2020-01-14
申请号：US15884407
申请日：2018-01-31
Applicant: PHISON ELECTRONICS CORP.
Inventor： Yu-Hsiang Lin , Shao-Wei Yen , Cheng-Che Yang , Kuo-Hsin Lai
Abstract: A decoding method for a memory storage device including a rewritable non-volatile memory module is provided according to an exemplary embodiment of the invention. The method includes: reading at least one memory cells by using at least one read voltage level to obtain a codeword; performing a parity check operation on the codeword by an error checking and correcting circuit to generate a syndrome sum corresponding to the codeword; and dynamically adjusting a first parameter used by the error checking and correcting circuit in a first decoding operation based on whether the syndrome sum is less than a first threshold value and performing the first decoding operation on the codeword by the error checking and correcting circuit by using the first parameter.
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公开(公告)号：US10116335B2
公开(公告)日：2018-10-30
申请号：US15188995
申请日：2016-06-22
Applicant: PHISON ELECTRONICS CORP.
Inventor： Yu-Hsiang Lin , Cheng-Che Yang , Shao-Wei Yen , Kuo-Hsin Lai
Abstract: A data processing method, a memory storage device and a memory control circuit unit are provided. The method includes: receiving first write data; performing a first stage encoding operation of a low-density parity-check (LDPC) code on the first write data and generating first transition data; performing a second stage encoding operation of the LDPC code on the first transition data and generating a first error correcting code (ECC); receiving second write data; and performing the first stage encoding operation of the LDPC code on the second write data during a time period of performing the second stage encoding operation of the LDPC code on the first transition data. Accordingly, the data processing efficiency corresponding to the LDPC code can be improved.
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