公开(公告)号：US09858366B2

公开(公告)日：2018-01-02

申请号：US13723114

申请日：2012-12-20

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kuo-Yi Cheng ,  Yi-Hong Huang ,  Huang-Heng Cheng

IPC: G06F17/50 ,  G06F13/16 ,  G06F13/10 ,  G06F3/06 ,  G06F12/02 ,  G06F12/06 ,  G06F9/455

CPC classification number: G06F17/5022 ,  G06F3/0679 ,  G06F9/455 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0638 ,  G06F13/105 ,  G06F13/1694 ,  G06F17/5027 ,  G06F2212/151 ,  H01L2924/1438 ,  H01L2924/14511

Abstract: A simulating method for a flash memory and a simulator using the simulating method are provided. The simulator is configured to couple to a memory controller. The simulating method includes: setting a predetermined response condition; providing multiple command sets, wherein each of the command sets corresponds to a memory type; receiving a first command from the memory controller; identifying a second command in the command sets according to the first command; determining if the second command matches the predetermined response condition; obtaining a first signal corresponding to the second command according to the predetermined response condition; and, transmitting the first signal to the memory controller. Accordingly, the usage of the simulator is flexible.

公开(公告)号：US09703698B2

公开(公告)日：2017-07-11

申请号：US13935572

申请日：2013-07-05

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kuo-Yi Cheng ,  Wei Lin ,  Kim-Hon Wong ,  Hao-Zhi Lee ,  Hung-Chun Lin ,  Chun-Yen Chang

IPC: G06F12/00 ,  G06F12/02 ,  G11C11/56 ,  G11C29/00 ,  G11C7/04

CPC classification number: G06F12/0246 ,  G06F2212/7202 ,  G11C7/04 ,  G11C11/5628 ,  G11C29/82

Abstract: A data writing method for writing data into a physical erasing unit and a memory controller and a memory storage apparatus using the data writing method are provided. The method includes dividing the data into a plurality of information frames in a unit of one physical programming unit. The method also includes writing the information frames in sequence into at least one physical programming unit constituted by memory cells disposed on at least one first word line and programming the storage state of memory cells disposed on at least one second word line following the first word line to an auxiliary pattern. Accordingly, the method effectively prevents data stored in the physical erasing unit, which is not full of data, from being lost due to a high temperature.

公开(公告)号：US08737126B2

公开(公告)日：2014-05-27

申请号：US13653424

申请日：2012-10-17

Applicant: Phison Electronics Corp.

Inventor： Wei Lin ,  Kuo-Yi Cheng ,  Chun-Yen Chang

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/10 ,  G11C7/00

CPC classification number: G11C16/10 ,  G11C7/00 ,  G11C11/5628 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/3468 ,  G11C16/3495 ,  G11C2211/5621

Abstract: A data writing method for writing data into a memory cell of a rewritable non-volatile memory module, and a memory controller and a memory storage apparatus using the same area provided. The method includes recording a wear degree of the memory cell and adjusting an initial write voltage and a write voltage pulse time corresponding to the memory cell based on the wear degree thereof. The method further includes programming the memory cell by applying the initial write voltage and the write voltage pulse time, thereby writing the data into the memory cell. Accordingly, data can be accurately stored into the rewritable non-volatile memory module by the method.

Abstract translation: 一种用于将数据写入可重写非易失性存储器模块的存储单元的数据写入方法，以及使用相同区域的存储器控​​制器和存储器存储装置。 该方法包括记录存储单元的磨损程度，并且基于其磨损程度调整对应于存储单元的初始写入电压和写入电压脉冲时间。 该方法还包括通过施加初始写入电压和写入电压脉冲时间对存储器单元进行编程，从而将数据写入存储单元。 因此，可以通过该方法将数据精确地存储到可重写非易失性存储器模块中。

公开(公告)号：US09257204B2

公开(公告)日：2016-02-09

申请号：US14018436

申请日：2013-09-05

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  Siu-Tung Lam ,  Tzung-Lin Wu ,  Kuo-Yi Cheng

IPC: G11C29/00 ,  G11C29/50 ,  G11C16/26 ,  G11C29/02 ,  G11C16/34 ,  G11C16/00

CPC classification number: G11C29/50004 ,  G11C16/00 ,  G11C16/26 ,  G11C16/3459 ,  G11C29/021 ,  G11C29/028

Abstract: A read voltage setting method for a rewritable non-volatile memory module is provided. The method includes: reading test data stored in memory cells of a word line to obtain a corresponding critical voltage distribution and identifying a default read voltage corresponding to the word line based on the corresponding critical voltage distribution; applying a plurality of test read voltages obtained according to the default read voltage to the word line to read a plurality of test page data; and determining an optimized read voltage corresponding to the word line according to the minimum error bit number among a plurality of error bit numbers of the test page data. The method further includes calculating a difference value between the default read voltage and the optimized read voltage as a read voltage adjustment value corresponding to the word line and recording the read voltage adjustment value in a retry table.

Abstract translation: 提供了一种用于可重写非易失性存储器模块的读取电压设置方法。 该方法包括：读取存储在字线的存储单元中的测试数据，以获得相应的临界电压分布，并基于相应的临界电压分布识别与字线对应的默认读取电压; 将根据所述默认读取电压获得的多个测试读取电压施加到所述字线以读取多个测试页面数据; 以及根据所述测试页数据的多个错误位数中的最小误差位数确定与所述字线对应的优化读取电压。 该方法还包括计算默认读取电压和优化读取电压之间的差值作为对应于字线的读取电压调整值，并将读取电压调整值记录在重试表中。

公开(公告)号：US20150095741A1

公开(公告)日：2015-04-02

申请号：US14109959

申请日：2013-12-18

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Shao-Wei Yen ,  Yu-Hsiang Lin ,  Kuo-Hsin Lai ,  Kuo-Yi Cheng

IPC: G06F11/10

CPC classification number: G06F11/1008 ,  G06F11/1048

Abstract: A decoding method, a memory storage device and a memory controlling circuit unit are provided. The method includes: reading memory cells according to a first reading voltage to obtain first verifying bits; executing a decoding procedure including a probability decoding algorithm according to the first verifying bits to obtain first decoded bits, and determining whether a decoding is successful by using the decoded bits; if the decoding is failed, reading the memory cells according to a second reading voltage to obtain second verifying bits, and executing the decoding procedure according to the second verifying bits to obtain second decoded bits. The second reading voltage is different from the first reading voltage, and the number of the second reading voltage is equal to the number of the first reading voltage. Accordingly, the ability for correcting errors is improved.

Abstract translation: 提供了解码方法，存储器存储装置和存储器控制电路单元。 该方法包括：根据第一读取电压读取存储器单元以获得第一验证位; 执行包括根据第一验证位的概率解码算法的解码过程以获得第一解码比特，并且通过使用解码比特来确定解码是否成功; 如果解码失败，则根据第二读取电压读取存储器单元以获得第二验证位，并且根据第二验证位执行解码过程以获得第二解码位。 第二读取电压与第一读取电压不同，第二读取电压的数量等于第一读取电压的数量。 因此，能够提高校正误差的能力。

公开(公告)号：US20140325118A1

公开(公告)日：2014-10-30

申请号：US13935572

申请日：2013-07-05

Applicant: Phison Electronics Corp.

Inventor： Kuo-Yi Cheng ,  Wei Lin ,  Kim-Hon Wong ,  Hao-Zhi Lee ,  Hung-Chun Lin ,  Chun-Yen Chang

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7202 ,  G11C7/04 ,  G11C11/5628 ,  G11C29/82

Abstract: A data writing method for writing data into a physical erasing unit and a memory controller and a memory storage apparatus using the data writing method are provided. The method includes dividing the data into a plurality of information frames in a unit of one physical programming unit. The method also includes writing the information frames in sequence into at least one physical programming unit constituted by memory cells disposed on at least one first word line and programming the storage state of memory cells disposed on at least one second word line following the first word line to an auxiliary pattern. Accordingly, the method effectively prevents data stored in the physical erasing unit, which is not full of data, from being lost due to a high temperature.

Abstract translation: 提供了一种用于将数据写入物理擦除单元和存储器控制器以及使用数据写入方法的存储器装置的数据写入方法。 该方法包括以一个物理编程单元为单位将数据划分成多个信息帧。 该方法还包括将信息帧顺序地写入至少一个物理编程单元，该物理编程单元由设置在至少一个第一字线上的存储单元构成，并且对位于第一字线之后的至少一个第二字线上的存储单元的存储状态进行编程 到辅助模式。 因此，该方法有效地防止存储在不充满数据的物理擦除单元中的数据由于高温而丢失。

公开(公告)号：US20140129206A1

公开(公告)日：2014-05-08

申请号：US13723114

申请日：2012-12-20

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kuo-Yi Cheng ,  Yi-Hong Huang ,  Huang-Heng Cheng

IPC: G06F9/455

CPC classification number: G06F17/5022 ,  G06F3/0679 ,  G06F9/455 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0638 ,  G06F13/105 ,  G06F13/1694 ,  G06F17/5027 ,  G06F2212/151 ,  H01L2924/1438 ,  H01L2924/14511

Abstract: A simulating method for a flash memory and a simulator using the simulating method are provided. The simulator is configured to couple to a memory controller. The simulating method includes: setting a predetermined response condition; providing multiple command sets, wherein each of the command sets corresponds to a memory type; receiving a first command from the memory controller; identifying a second command in the command sets according to the first command; determining if the second command matches the predetermined response condition; obtaining a first signal corresponding to the second command according to the predetermined response condition; and, transmitting the first signal to the memory controller. Accordingly, the usage of the simulator is flexible.

Abstract translation: 提供了一种用于闪存的模拟方法和使用模拟方法的模拟器。 模拟器被配置为耦合到存储器控制器。 模拟方法包括：设定预定的响应条件; 提供多个命令集，其中每个命令集对应于存储器类型; 从所述存储器控制器接收第一命令; 根据第一命令识别命令集中的第二命令; 确定所述第二命令是否匹配所述预定响应条件; 根据预定的响应条件获得与第二命令相对应的第一信号; 以及将所述第一信号发送到所述存储器控制器。 因此，模拟器的使用是灵活的。

公开(公告)号：US09348693B2

公开(公告)日：2016-05-24

申请号：US13901239

申请日：2013-05-23

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kuo-Yi Cheng ,  Chih-Kang Yeh

IPC: G11C29/00 ,  G06F11/10 ,  H03M13/05 ,  H03M13/27

CPC classification number: G06F11/1068 ,  H03M13/05 ,  H03M13/27

Abstract: A storage apparatus is provided. The controller of the storage apparatus includes an error correction module and a data disordering module. The error correction module is configured to perform an error correction procedure for a data packet to be written into a flash memory module of the storage apparatus for generating sequence data codes containing the data packet and corresponding error correcting codes, wherein the data packet includes a data area recording data to be written and a spare area recording data related to the data packet. The data disordering module is configured to convert the sequence data codes into non-sequence data codes, wherein the data of the data area and the spare area and error correcting codes are dispersed in the non-sequence data codes. Accordingly, it is possible to effectively increase the safety of the data packet.

Abstract translation: 提供一种存储装置。 存储装置的控制器包括纠错模块和数据混乱模块。 纠错模块被配置为对要写入存储装置的闪速存储器模块的数据分组执行纠错过程，用于产生包含数据分组和对应的纠错码的序列数据代码，其中数据分组包括数据 要写入的区域记录数据和与数据分组相关的备用区域记录数据。 数据无序模块被配置为将序列数据代码转换为非序列数据代码，其中数据区域和备用区域的数据和纠错码分散在非序列数据代码中。 因此，可以有效地提高数据包的安全性。

公开(公告)号：US09245636B2

公开(公告)日：2016-01-26

申请号：US13917621

申请日：2013-06-13

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  Kuo-Yi Cheng

IPC: G11C11/00 ,  G11C16/26 ,  H01L29/792 ,  H01L27/115 ,  G11C11/56 ,  G11C16/04

CPC classification number: G11C16/14 ,  G11C11/5642 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/26 ,  H01L27/11582 ,  H01L29/7926

Abstract: A NAND flash memory unit, an operating method and a reading method are provided. The NAND flash memory unit includes a plurality of gate layers, a tunnel layer, a charge trapping layer, a conductor layer and a second dielectric layer. A first dielectric layer is included between two adjacent gate layers among the gate layers. The tunnel layer, the charge trapping layer, the conductor layer, and the second dielectric layer penetrate the gate layers. The charge trapping layer is disposed between the tunnel layer and the gate layers, and the second dielectric layer is disposed between the conductor layer and the tunnel layer. Therefore, an erasing speed may be increased; the charge trapping layer may be repaired; the controllability of the gate layers may be increased.

Abstract translation: 提供NAND闪存单元，操作方法和读取方法。 NAND闪存单元包括多个栅极层，隧道层，电荷俘获层，导体层和第二介电层。 在栅极层之间的两个相邻栅极层之间包括第一介电层。 隧道层，电荷俘获层，导体层和第二介电层穿透栅极层。 电荷捕获层设置在隧道层和栅极层之间，第二介电层设置在导体层和隧道层之间。 因此，可以增加擦除速度; 电荷捕获层可以被修复; 可以提高栅极层的可控性。

公开(公告)号：US20140293696A1

公开(公告)日：2014-10-02

申请号：US13901571

申请日：2013-05-24

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Tien-Ching Wang ,  Kuo-Hsin Lai ,  Yu-Cheng Hsu ,  Kuo-Yi Cheng

IPC: G11C16/26

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/3436 ,  G11C16/349

Abstract: A data reading method for a rewritable non-volatile memory module is provided. The method includes applying a test voltage to a word line of the rewritable non-volatile memory module to read a plurality of verification bit data. The method also includes calculating a variation of bit data identified as a first status among the verification bit data, obtaining a new read voltage value set based on the variation, and updating a threshold voltage set for the word line with the new read voltage value set. The method further includes using the updated threshold voltage set to read data from a physical page formed by memory cells connected to the word line. Accordingly, storage states of memory cells in the rewritable non-volatile memory module can be identified correctly, thereby preventing data stored in the memory cells from losing.

Abstract translation: 提供了一种可重写非易失性存储器模块的数据读取方法。 该方法包括将测试电压施加到可重写非易失性存储器模块的字线以读取多个验证位数据。 该方法还包括计算在验证位数据中识别为第一状态的位数据的变化，获得基于该变化设置的新的读取电压值，并且用新的读取电压值集更新用于字线的阈值电压 。 该方法还包括使用更新的阈值电压来从连接到字线的存储器单元形成的物理页读取数据。 因此，可以正确地识别可重写非易失性存储器模块中的存储单元的存储状态，从而防止存储在存储单元中的数据丢失。