公开(公告)号：US20190278480A1

公开(公告)日：2019-09-12

申请号：US15956749

申请日：2018-04-19

Applicant: PHISON ELECTRONICS CORP.

Inventor： Siu-Tung Lam ,  Ming-Yen Lee ,  Kuo-Lung Lee

IPC: G06F3/06 ,  G06F12/02 ,  G06F11/10 ,  G11C29/52 ,  G06F15/18

Abstract: A block management method, a memory control circuit unit and a memory storage apparatus for managing a plurality of physical blocks are provided. The method includes reading user data from a first physical block among physical blocks to obtain a plurality of parameters; inputting the parameters corresponding to the first physical block into a machine learning based block recognizer to group the first physical block into a first block group or a second block group according to an output result of the machine learning based block recognizer; establishing a first and second block mapping tables; mapping logical addresses of the first and second block mapping tables to the physical blocks belonging to the first and second block groups. The parameters may comprise at least one of a read busy time parameter, an error bit position parameter and a storage retention parameter. A machine learning operation may be performed using first and second test physical blocks, and corresponding parameters, as training data. A usage status may be determined according to the parameters, and blocks with a usage status of good may be used first to evenly use all the physical blocks.

公开(公告)号：US09496041B2

公开(公告)日：2016-11-15

申请号：US14692759

申请日：2015-04-22

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  An-Cheng Liu ,  Siu-Tung Lam

IPC: G11C16/10 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3459

Abstract: A memory programming method for a rewritable non-volatile memory module having memory cells is provided. The memory programming method includes: performing a first programming process on the memory cells according to write data and obtaining a first programming result of the first programming process; grouping the memory cells into programming groups according to the first programming result; and performing a second programming process on the memory cells according to the write data. The second programming process includes: programming a first programming group among the programming groups by using a first program voltage; and programming a second programming group among the programming groups by using a second program voltage. The first program voltage and the second program voltage are different. Moreover, a memory control circuit unit and a memory storage device are provided.

Abstract translation: 提供了一种用于具有存储器单元的可重写非易失性存储器模块的存储器编程方法。 存储器编程方法包括：根据写数据对存储器单元执行第一编程处理并获得第一编程处理的第一编程结果; 根据第一编程结果将存储器单元分组成编程组; 以及根据写入数据对存储器单元执行第二编程处理。 第二编程过程包括：通过使用第一编程电压对编程组中的第一编程组进行编程; 以及通过使用第二编程电压来编程所述编程组中的第二编程组。 第一编程电压和第二编程电压不同。 此外，提供存储器控制电路单元和存储器存储装置。

公开(公告)号：US09529666B2

公开(公告)日：2016-12-27

申请号：US14295355

申请日：2014-06-04

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Shao-Wei Yen ,  Yu-Hsiang Lin ,  Tien-Ching Wang ,  Kuo-Hsin Lai ,  Siu-Tung Lam

IPC: G11C29/00 ,  G06F11/10 ,  G11C29/42 ,  H03M13/37 ,  H03M13/00 ,  H03M13/11 ,  H03M13/15 ,  H03M13/23

CPC classification number: G06F11/1008 ,  G06F11/1012 ,  G11C29/42 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/152 ,  H03M13/23 ,  H03M13/3715 ,  H03M13/3723 ,  H03M13/6325

Abstract: A decoding method, a memory storage device and a memory controlling circuit are provided. The decoding method includes: sending a read command sequence configured to read the memory cells, so as to obtain a plurality of first verification bits; executing a first decoding procedure according to the first verification bits, and determining whether a first valid codeword is generated; if the first valid codeword is not generated, sending another read command sequence configured to obtain a plurality of second verification bits; calculating a total number of the memory cells conforming to a specific condition according to the second verification bits; obtaining a channel reliability message according to the total number; and executing a second decoding procedure according to the channel reliability message. Accordingly, a correcting ability of decoding may be improved.

Abstract translation: 提供了解码方法，存储器存储装置和存储器控制电路。 解码方法包括：发送配置为读取存储单元的读命令序列，以获得多个第一验证位; 执行根据所述第一验证比特的第一解码过程，以及确定是否生成第一有效码字; 如果不产生第一有效码字，则发送另一读取命令序列，被配置为获得多个第二验证比特; 根据第二验证位计算符合特定条件的存储单元的总数; 根据总数获取信道可靠性消息; 以及根据信道可靠性消息执行第二解码过程。 因此，可以提高解码的校正能力。

公开(公告)号：US09257204B2

公开(公告)日：2016-02-09

申请号：US14018436

申请日：2013-09-05

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  Siu-Tung Lam ,  Tzung-Lin Wu ,  Kuo-Yi Cheng

IPC: G11C29/00 ,  G11C29/50 ,  G11C16/26 ,  G11C29/02 ,  G11C16/34 ,  G11C16/00

CPC classification number: G11C29/50004 ,  G11C16/00 ,  G11C16/26 ,  G11C16/3459 ,  G11C29/021 ,  G11C29/028

Abstract: A read voltage setting method for a rewritable non-volatile memory module is provided. The method includes: reading test data stored in memory cells of a word line to obtain a corresponding critical voltage distribution and identifying a default read voltage corresponding to the word line based on the corresponding critical voltage distribution; applying a plurality of test read voltages obtained according to the default read voltage to the word line to read a plurality of test page data; and determining an optimized read voltage corresponding to the word line according to the minimum error bit number among a plurality of error bit numbers of the test page data. The method further includes calculating a difference value between the default read voltage and the optimized read voltage as a read voltage adjustment value corresponding to the word line and recording the read voltage adjustment value in a retry table.

Abstract translation: 提供了一种用于可重写非易失性存储器模块的读取电压设置方法。 该方法包括：读取存储在字线的存储单元中的测试数据，以获得相应的临界电压分布，并基于相应的临界电压分布识别与字线对应的默认读取电压; 将根据所述默认读取电压获得的多个测试读取电压施加到所述字线以读取多个测试页面数据; 以及根据所述测试页数据的多个错误位数中的最小误差位数确定与所述字线对应的优化读取电压。 该方法还包括计算默认读取电压和优化读取电压之间的差值作为对应于字线的读取电压调整值，并将读取电压调整值记录在重试表中。

公开(公告)号：US20150293811A1

公开(公告)日：2015-10-15

申请号：US14295355

申请日：2014-06-04

Applicant: Phison Electronics Corp.

Inventor： Wei Lin ,  Shao-Wei Yen ,  Yu-Hsiang Lin ,  Tien-Ching Wang ,  Kuo-Hsin Lai ,  Siu-Tung Lam

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/11

CPC classification number: G06F11/1008 ,  G06F11/1012 ,  G11C29/42 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/152 ,  H03M13/23 ,  H03M13/3715 ,  H03M13/3723 ,  H03M13/6325

Abstract: A decoding method, a memory storage device and a memory controlling circuit are provided. The decoding method includes: sending a read command sequence configured to read the memory cells, so as to obtain a plurality of first verification bits; executing a first decoding procedure according to the first verification bits, and determining whether a first valid codeword is generated; if the first valid codeword is not generated, sending another read command sequence configured to obtain a plurality of second verification bits; calculating a total number of the memory cells conforming to a specific condition according to the second verification bits; obtaining a channel reliability message according to the total number; and executing a second decoding procedure according to the channel reliability message. Accordingly, a correcting ability of decoding may be improved.

Abstract translation: 提供了解码方法，存储器存储装置和存储器控制电路。 解码方法包括：发送配置为读取存储单元的读命令序列，以获得多个第一验证位; 执行根据所述第一验证比特的第一解码过程，以及确定是否生成第一有效码字; 如果不产生第一有效码字，则发送另一读取命令序列，被配置为获得多个第二验证比特; 根据第二验证位计算符合特定条件的存储单元的总数; 根据总数获取信道可靠性消息; 以及根据信道可靠性消息执行第二解码过程。 因此，可以提高解码的校正能力。

公开(公告)号：US20150006983A1

公开(公告)日：2015-01-01

申请号：US14018436

申请日：2013-09-05

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  Siu-Tung Lam ,  Tzung-Lin Wu ,  Kuo-Yi Cheng

IPC: G11C29/50 ,  G11C16/26

CPC classification number: G11C29/50004 ,  G11C16/00 ,  G11C16/26 ,  G11C16/3459 ,  G11C29/021 ,  G11C29/028

Abstract: A read voltage setting method for a rewritable non-volatile memory module is provided. The method includes: reading test data stored in memory cells of a word line to obtain a corresponding critical voltage distribution and identifying a default read voltage corresponding to the word line based on the corresponding critical voltage distribution; applying a plurality of test read voltages obtained according to the default read voltage to the word line to read a plurality of test page data; and determining an optimized read voltage corresponding to the word line according to the minimum error bit number among a plurality of error bit numbers of the test page data. The method further includes calculating a difference value between the default read voltage and the optimized read voltage as a read voltage adjustment value corresponding to the word line and recording the read voltage adjustment value in a retry table.

Abstract translation: 提供了一种用于可重写非易失性存储器模块的读取电压设置方法。 该方法包括：读取存储在字线的存储单元中的测试数据，以获得相应的临界电压分布，并基于相应的临界电压分布识别与字线对应的默认读取电压; 将根据所述默认读取电压获得的多个测试读取电压施加到所述字线以读取多个测试页面数据; 以及根据所述测试页数据的多个错误位数中的最小误差位数确定与所述字线对应的优化读取电压。 该方法还包括计算默认读取电压和优化读取电压之间的差值作为对应于字线的读取电压调整值，并将读取电压调整值记录在重试表中。

公开(公告)号：US20160240256A1

公开(公告)日：2016-08-18

申请号：US14692759

申请日：2015-04-22

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  An-Cheng Liu ,  Siu-Tung Lam

IPC: G11C16/10 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3459

Abstract: A memory programming method for a rewritable non-volatile memory module having memory cells is provided. The memory programming method includes: performing a first programming process on the memory cells according to write data and obtaining a first programming result of the first programming process; grouping the memory cells into programming groups according to the first programming result; and performing a second programming process on the memory cells according to the write data. The second programming process includes: programming a first programming group among the programming groups by using a first program voltage; and programming a second programming group among the programming groups by using a second program voltage. The first program voltage and the second program voltage are different. Moreover, a memory control circuit unit and a memory storage device are provided.

Abstract translation: 提供了一种用于具有存储器单元的可重写非易失性存储器模块的存储器编程方法。 存储器编程方法包括：根据写数据对存储器单元执行第一编程处理并获得第一编程处理的第一编程结果; 根据第一编程结果将存储器单元分组成编程组; 以及根据写入数据对存储器单元执行第二编程处理。 第二编程过程包括：通过使用第一编程电压对编程组中的第一编程组进行编程; 以及通过使用第二编程电压来编程所述编程组中的第二编程组。 第一编程电压和第二编程电压不同。 此外，提供存储器控制电路单元和存储器存储装置。

公开(公告)号：US20160232053A1

公开(公告)日：2016-08-11

申请号：US14693885

申请日：2015-04-23

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  An-Cheng Liu ,  Siu-Tung Lam

IPC: G06F11/10 ,  G11C29/50 ,  G11C29/52

CPC classification number: G06F11/108 ,  G06F11/1072 ,  G11C5/148 ,  G11C11/5628 ,  G11C16/12 ,  G11C16/3459 ,  G11C29/021 ,  G11C29/028 ,  G11C29/42 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: The present disclosure provides a memory management method for a rewritable non-volatile memory module. The rewritable non-volatile memory module includes physical programming units, each of which includes multiple bits. The memory management method includes: identifying a first physical programming unit by applying a predetermined read voltage, where the first physical programming unit is identified as in a fully-erased status; identifying a second and a third physical programming units which are programmed before the first physical programming unit; acquiring status data of the second and the third physical programming unit; computing a difference of the status data between the second and the third physical programming unit; if the difference is larger than a threshold, identifying the second physical programming unit as in a program failure status.

Abstract translation: 本公开提供了一种用于可重写非易失性存储器模块的存储器管理方法。 可重写非易失性存储器模块包括物理编程单元，每个物理编程单元包括多个位。 存储器管理方法包括：通过施加预定的读取电压来识别第一物理编程单元，其中第一物理编程单元被识别为完全擦除状态; 识别在第一物理编程单元之前编程的第二和第三物理编程单元; 获取第二和第三物理编程单元的状态数据; 计算第二和第三物理编程单元之间的状态数据的差异; 如果差异大于阈值，则在程序故障状态中识别第二物理编程单元。

公开(公告)号：US09312013B1

公开(公告)日：2016-04-12

申请号：US14693876

申请日：2015-04-23

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  An-Cheng Liu ,  Siu-Tung Lam

IPC: G11C16/04 ,  G11C16/14 ,  G11C16/34

CPC classification number: G11C16/3495 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3445

Abstract: A configuration method of erase operation, a memory controlling circuit unit, and a memory storage device are provided. The method includes: determining whether a first use state of a first physical unit conforms to a first default state; and if the first use state conforms to the first default state, adjusting a first erase operation corresponding to the first physical unit from using a first mode to a second mode. Thereby, a threshold voltage distribution of memory cells in an erase state may be maintained in a proper range.

Abstract translation: 提供擦除操作的配置方法，存储器控制电路单元和存储器存储设备。 该方法包括：确定第一物理单元的第一使用状态是否符合第一默认状态; 并且如果第一使用状态符合第一默认状态，则调整与第一物理单元相对应的第一擦除操作，从第一模式到第二模式。 因此，可以将擦除状态的存储单元的阈值电压分布保持在适当的范围内。

公开(公告)号：US11139044B2

公开(公告)日：2021-10-05

申请号：US16150263

申请日：2018-10-02

Applicant: PHISON ELECTRONICS CORP.

Inventor： Siu-Tung Lam ,  Chih-Hung Chiu ,  Kun-Tsung Lo ,  Chao-Kai Zhang

IPC: G11C29/42 ,  G11C29/12 ,  G11C29/44

Abstract: A memory testing method and a memory testing system. The memory testing system includes a host system and a testing device. The host system includes a processor. The testing device is coupled to the host system and a rewritable non-volatile memory module. A first memory controlling circuit unit corresponding to a first type memory storage device in the testing device tests the rewritable non-volatile memory module to obtain first test information. A second memory controlling circuit unit corresponding to a second type memory storage device in the testing device tests the rewritable non-volatile memory module to obtain second test information according to the first test information. The processor determines that whether the rewritable non-volatile memory module is applicable to the second type memory storage device or not according to the first test information and the second test information.