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公开(公告)号:US20210357145A1
公开(公告)日:2021-11-18
申请号:US16920446
申请日:2020-07-03
Applicant: PHISON ELECTRONICS CORP.
Inventor: Wei-Cheng Li , Yu-Chung Shen , Wei-Liang Huang , Chao-Kai Zhang
IPC: G06F3/06
Abstract: A data writing method for a rewritable non-volatile memory module is provided according to embodiments of the disclosure. The method includes: writing first-type data into a first physical unit at a first write speed; and writing second-type data into a second physical unit at a second write speed. The first-type data is different from the second-type data, and the first write speed is different from the second write speed.
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公开(公告)号:US11139044B2
公开(公告)日:2021-10-05
申请号:US16150263
申请日:2018-10-02
Applicant: PHISON ELECTRONICS CORP.
Inventor: Siu-Tung Lam , Chih-Hung Chiu , Kun-Tsung Lo , Chao-Kai Zhang
Abstract: A memory testing method and a memory testing system. The memory testing system includes a host system and a testing device. The host system includes a processor. The testing device is coupled to the host system and a rewritable non-volatile memory module. A first memory controlling circuit unit corresponding to a first type memory storage device in the testing device tests the rewritable non-volatile memory module to obtain first test information. A second memory controlling circuit unit corresponding to a second type memory storage device in the testing device tests the rewritable non-volatile memory module to obtain second test information according to the first test information. The processor determines that whether the rewritable non-volatile memory module is applicable to the second type memory storage device or not according to the first test information and the second test information.
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公开(公告)号:US20200066366A1
公开(公告)日:2020-02-27
申请号:US16150263
申请日:2018-10-02
Applicant: PHISON ELECTRONICS CORP.
Inventor: Siu-Tung Lam , Chih-Hung Chiu , Kun-Tsung Lo , Chao-Kai Zhang
Abstract: A memory testing method and a memory testing system. The memory testing system includes a host system and a testing device. The host system includes a processor. The testing device is coupled to the host system and a rewritable non-volatile memory module. A first memory controlling circuit unit corresponding to a first type memory storage device in the testing device tests the rewritable non-volatile memory module to obtain first test information. A second memory controlling circuit unit corresponding to a second type memory storage device in the testing device tests the rewritable non-volatile memory module to obtain second test information according to the first test information. The processor determines that whether the rewritable non-volatile memory module is applicable to the second type memory storage device or not according to the first test information and the second test information.
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