公开(公告)号：US12236132B2

公开(公告)日：2025-02-25

申请号：US17573567

申请日：2022-01-11

Applicant: PHISON ELECTRONICS CORP.

Inventor： Sebastien Jean ,  Ming-Jen Liang

IPC: G06F3/06

Abstract: A memory management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: sending a first operation command sequence to a rewritable non-volatile memory module to instruct a first memory module in the rewritable non-volatile memory module to perform a first operation; obtaining a first time threshold value corresponding to the first operation; updating a first counting value corresponding to the first memory module; and sending a first query command sequence to the rewritable non-volatile memory module to query a status of the first memory module, in response to that the first counting value reaches the first time threshold value.

公开(公告)号：US20250036308A1

公开(公告)日：2025-01-30

申请号：US18469561

申请日：2023-09-19

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kok-Yong Tan

IPC: G06F3/06

Abstract: A memory management method, a memory storage device, and a memory control circuit unit are provided. The method includes establishing a connection between the memory storage device and a host system; receiving a first request from the host system via the connection; detecting a status of the memory storage device in a time range according to the first request; and determining whether to use a memory in the host system according to the status.

公开(公告)号：US20240402943A1

公开(公告)日：2024-12-05

申请号：US18349962

申请日：2023-07-11

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yen Chen Yeh

IPC: G06F3/06

Abstract: A memory management method, a memory storage device, and a memory control circuit unit are disclosed. The method is for a rewritable non-volatile memory module including first type physical units and second type physical units. The first type physical units adopt a first operation mode. The second type physical units adopt a second operation mode. The method includes: grouping a part of physical units in the second type physical units to a first reserved region and a second reserved region, and the physical units belonging to the first reserved region and the second reserved region are reserved for usage in a data merging operation; and performing a first data merging operation which includes: collecting first data from a source unit; selecting a target unit from the first reserved region or the second reserved region according to attribute of the source unit; and storing the first data to the target unit.

公开(公告)号：US20240312949A1

公开(公告)日：2024-09-19

申请号：US18306971

申请日：2023-04-25

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kang-Yun Yang ,  Yang-Tse Hung ,  Chao-Cheng Ku ,  Li-Yuan Lee

IPC: H01L23/00 ,  G11C5/06 ,  G11C16/14

CPC classification number: H01L24/49 ,  G11C5/06 ,  G11C16/14 ,  H01L2224/4912

Abstract: A layout structure of differential lines, a memory storage device and a memory control circuit unit are provided. The layout structure of the differential lines includes a wiring layer, a first wire and a second wire. The first wire is arranged on the wiring layer and configured to transmit a first differential signal. The second wire is arranged on the wiring layer and configured to transmit a second differential signal. A first end of the first wire and a first end of the second wire are coupled to a first electrical component. A second end of the first wire and a second end of the second wire are coupled to a second electrical component. The first end of the first wire has a first bending structure. One of the second end of the first wire and the second end of the second wire has a second bending structure.

公开(公告)号：US20240304259A1

公开(公告)日：2024-09-12

申请号：US18298335

申请日：2023-04-10

Applicant: PHISON ELECTRONICS CORP.

Inventor： Po-Cheng Su ,  Po-Hao Chen ,  Yu-Cheng Hsu ,  Wei Lin

IPC: G11C16/26 ,  G11C16/08 ,  G11C16/34

CPC classification number: G11C16/26 ,  G11C16/08 ,  G11C16/3404

Abstract: A voltage prediction method, a memory storage device and a memory control circuit unit are disclosed. The method includes: reading a plurality of memory cells in a rewritable non-volatile memory module by using a first read voltage level to obtain count information, and the first read voltage level is configured to distinguish a first state and a second state adjacent to each other in a threshold voltage distribution of the memory cells, and the count information reflects a total number of first memory cells meeting a target condition among the memory cells; and predicting a second read voltage level according to the count information, and the second read voltage level is configured to distinguish a third state and a fourth state adjacent to each other in the threshold voltage distribution.

公开(公告)号：US12086419B2

公开(公告)日：2024-09-10

申请号：US17866569

申请日：2022-07-18

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh

IPC: G06F3/06

CPC classification number: G06F3/0616 ,  G06F3/0652 ,  G06F3/0679

Abstract: A partial erasing management method, a memory storage device, and a memory control circuit unit are provided. The method includes: performing a first partial erasing operation on a first physical region among multiple physical regions in a first physical erasing unit to erase first data in the first physical region; after performing the first partial erasing operation on the first physical region, performing a first programming operation on the first physical region to store second data into the first physical region; and in response to at least one of the first partial erasing operation and the first programming operation, updating first status information related to the first physical region.

公开(公告)号：US12008242B2

公开(公告)日：2024-06-11

申请号：US17983407

申请日：2022-11-09

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yi-Chung Chen ,  Ming-Chien Huang

IPC: G06F3/06 ,  G11C11/4076

CPC classification number: G06F3/0614 ,  G06F3/0629 ,  G06F3/0673 ,  G11C11/4076

Abstract: A signal calibration method, a memory storage device, and a memory control circuit unit are provided. The signal calibration method includes: generating a clock signal and a data strobe signal according to an internal clock signal; respectively transmitting the clock signal and the data strobe signal to a target volatile memory module among multiple volatile memory modules through a first signal path and a second signal path; obtaining a shift value between the data strobe signal and the clock signal at the target volatile memory module; and storing an initial delay setting of the data strobe signal according to delay information of the data strobe signal in response to the shift value being greater than a threshold value.

公开(公告)号：US20240126313A1

公开(公告)日：2024-04-18

申请号：US18079900

申请日：2022-12-13

Applicant: PHISON ELECTRONICS CORP.

Inventor： Po-Chih Ku

IPC: G06F1/3234 ,  G06F1/3296

CPC classification number: G06F1/3275 ,  G06F1/3296

Abstract: A regulator circuit module, a memory storage device, and a voltage control method are disclosed. The method includes: generating an output voltage according to an input voltage by a driving circuit; generating a feedback voltage according to the output voltage; controlling the driving circuit to adjust the output voltage according to the feedback voltage by a regulator circuit; compensating an output of the regulator circuit by a compensating circuit; and activating or deactivating the compensating circuit according to an input bypass-voltage of a switch circuit.

公开(公告)号：US11809706B2

公开(公告)日：2023-11-07

申请号：US17349918

申请日：2021-06-17

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yu-Siang Yang ,  Yu-Cheng Hsu ,  Tsai-Hao Kuo ,  Wei Lin ,  An-Cheng Liu

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0619 ,  G06F3/0655 ,  G06F3/0679

Abstract: A memory management method, a memory storage device, and a memory control circuit unit are provided. The method includes: reading first data from a first physical unit by using a first read voltage level according to first management information among multiple candidate management information; decoding the first data and recording first error bit information of the first data; and adjusting sorting information related to the candidate management information according to the first error bit information. The sorting information reflects a usage order of the candidate management information in a decoding operation.

公开(公告)号：US20230297464A1

公开(公告)日：2023-09-21

申请号：US17715050

申请日：2022-04-07

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kok-Yong Tan

IPC: G06F11/07 ,  G06F1/30 ,  G06F3/06

CPC classification number: G06F11/0793 ,  G06F1/30 ,  G06F11/073 ,  G06F3/0625 ,  G06F3/065 ,  G06F3/0689 ,  G06F3/0619

Abstract: An abnormal power loss recovery method, a memory control circuit unit, and a memory storage device are provided. The method is configured for a memory storage device including a rewritable non-volatile memory module having a plurality of super-physical units. The super-physical units include at least two physical erasing units, and each of the physical erasing units belongs to a different operation unit and includes a plurality of physical programming units. The method includes: reading data stored in a first super-physical unit without a corresponding RAID ECC code when a memory storage device is powered on again and detected as an abnormal power loss to obtain first data, and the first super-physical unit is a last super-physical unit to which data is written before the abnormal power loss occurs; and copying the first data to a second super-physical unit.