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公开(公告)号：US20230195361A1
公开(公告)日：2023-06-22
申请号：US17577012
申请日：2022-01-17
发明人： Shih-Jia Zeng , Po-Cheng Su , Chih-Wei Wang , Wei Lin
IPC分类号： G06F3/06
CPC分类号： G06F3/0655 , G06F3/0604 , G06F3/0679
摘要： A read disturb checking method, a memory storage device, and a memory control circuit unit are provided. The method includes: updating first and second read counts of a first physical unit group according to a total read count of a read operation performed on physical programming units in the first physical unit group; scanning at least one first physical programming unit in a currently read physical erasing unit in response to determining the first read account is greater than a first read count threshold to obtain a first error bit amount; scanning all physical programming units in at least one first physical erasing unit in the first physical unit group in response to determining the second read account is greater than a second read count threshold to obtain a second error bit amount; performing a read disturb prevention operation according to the first or second error bit amount.
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公开(公告)号：US20240304259A1
公开(公告)日：2024-09-12
申请号：US18298335
申请日：2023-04-10
发明人： Po-Cheng Su , Po-Hao Chen , Yu-Cheng Hsu , Wei Lin
CPC分类号： G11C16/26 , G11C16/08 , G11C16/3404
摘要： A voltage prediction method, a memory storage device and a memory control circuit unit are disclosed. The method includes: reading a plurality of memory cells in a rewritable non-volatile memory module by using a first read voltage level to obtain count information, and the first read voltage level is configured to distinguish a first state and a second state adjacent to each other in a threshold voltage distribution of the memory cells, and the count information reflects a total number of first memory cells meeting a target condition among the memory cells; and predicting a second read voltage level according to the count information, and the second read voltage level is configured to distinguish a third state and a fourth state adjacent to each other in the threshold voltage distribution.
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公开(公告)号：US11829644B2
公开(公告)日：2023-11-28
申请号：US17581858
申请日：2022-01-22
发明人： Po-Cheng Su , Chih-Wei Wang , Yu-Cheng Hsu , Wei Lin
CPC分类号： G06F3/0659 , G06F3/0619 , G06F3/0679
摘要： A memory control method, a memory storage device, and a memory control circuit unit are provided. The memory control method includes: receiving a read command from a host system; in response to a first physical erasing unit being a first type physical unit, sending a first operation command sequence to instruct a rewritable non-volatile memory module to read a first physical programming unit based on a first electronic configuration; and in response to the first physical erasing unit being a second type physical unit, sending a second operation command sequence to instruct the rewritable non-volatile memory module to read the first physical programming unit based on a second electronic configuration. The first electronic configuration is different from the second electronic configuration.
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公开(公告)号：US20230176783A1
公开(公告)日：2023-06-08
申请号：US17581858
申请日：2022-01-22
发明人： Po-Cheng Su , Chih-Wei Wang , Yu-Cheng Hsu , Wei Lin
IPC分类号： G06F3/06
CPC分类号： G06F3/0659 , G06F3/0619 , G06F3/0679
摘要： A memory control method, a memory storage device, and a memory control circuit unit are provided. The memory control method includes: receiving a read command from a host system; in response to a first physical erasing unit being a first type physical unit, sending a first operation command sequence to instruct a rewritable non-volatile memory module to read a first physical programming unit based on a first electronic configuration; and in response to the first physical erasing unit being a second type physical unit, sending a second operation command sequence to instruct the rewritable non-volatile memory module to read the first physical programming unit based on a second electronic configuration. The first electronic configuration is different from the second electronic configuration.
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公开(公告)号：US20240304235A1
公开(公告)日：2024-09-12
申请号：US18301275
申请日：2023-04-17
发明人： Po-Hao Chen , Po-Cheng Su , Shih-Jia Zeng , Yu-Cheng Hsu , Wei Lin
CPC分类号： G11C11/409 , G06F3/0679 , G11C16/26
摘要： A voltage calibration method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: reading first data from a first physical unit using a first read voltage level and reading second data from at least one second physical unit using a second read voltage level; obtaining count information reflecting a total number of memory cells meeting a default condition in the first physical unit and the at least one second physical unit according to the first data and the second data; and calibrating the first read voltage level according to the count information.
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公开(公告)号：US20240201857A1
公开(公告)日：2024-06-20
申请号：US18168573
申请日：2023-02-14
发明人： Po-Cheng Su , Yu-Cheng Hsu , Wei Lin
IPC分类号： G06F3/06
CPC分类号： G06F3/0613 , G06F3/0659 , G06F3/0679
摘要： A decoding method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: sending at least one read command sequence instructing to read a first physical unit in a rewritable non-volatile memory module; receiving response data from the rewritable non-volatile memory module, wherein the response data includes a plurality of identification bits, and the plurality of identification bits reflect a voltage variation of a first bit line where a first memory cell in the first physical unit is located during a discharge process; determining a decoding parameter corresponding to the first memory cell according to the plurality of identification bits; and decoding data read from the first memory cell according to the decoding parameter.
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公开(公告)号：US11797222B2
公开(公告)日：2023-10-24
申请号：US17577012
申请日：2022-01-17
发明人： Shih-Jia Zeng , Po-Cheng Su , Chih-Wei Wang , Wei Lin
IPC分类号： G06F3/06
CPC分类号： G06F3/0655 , G06F3/0604 , G06F3/0679
摘要： A read disturb checking method, a memory storage device, and a memory control circuit unit are provided. The method includes: updating first and second read counts of a first physical unit group according to a total read count of a read operation performed on physical programming units in the first physical unit group; scanning at least one first physical programming unit in a currently read physical erasing unit in response to determining the first read account is greater than a first read count threshold to obtain a first error bit amount; scanning all physical programming units in at least one first physical erasing unit in the first physical unit group in response to determining the second read account is greater than a second read count threshold to obtain a second error bit amount; performing a read disturb prevention operation according to the first or second error bit amount.
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