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    SEMICONDUCTOR WAFER AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
    1.
    发明申请
    SEMICONDUCTOR WAFER AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
    半导体晶体管及半导体器件制造方法

    公开(公告)号：US20120018726A1

    公开(公告)日：2012-01-26

    申请号：US13258884

    申请日：2010-03-23

    申请人： Yoshihiro Nakagawa ,  Koichi Nose ,  Koichiro Noguchi ,  Masamoto Tago ,  Shinichi Uchida ,  Yoshiyuki Sato

    发明人： Yoshihiro Nakagawa ,  Koichi Nose ,  Koichiro Noguchi ,  Masamoto Tago ,  Shinichi Uchida ,  Yoshiyuki Sato

    IPC分类号： H01L23/48 ,  H01L21/768

    CPC分类号： H01L22/32 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A semiconductor wafer in which a plurality of regions, designed to become semiconductor chips are provided in a matrix array with interposition of a dicing line(s) respectively separating the regions. The semiconductor wafer comprises: a plurality of test pads provided in an area(s) of the semiconductor wafer disposed between the semiconductor chips, inclusive of the dicing line(s); an inter-test pad interconnect(s) provided in parallel with the test pads in the area(s) of the semiconductor wafer disposed between the regions to become semiconductor chips; the inter-test pad interconnect(s) being connected to the test pads; and an inter-chip interconnect that interconnects at least two of the regions designed to become semiconductor chips; the inter-test pad interconnect being electrically connected to the inter-chip interconnect.

    摘要翻译： 设置成成为半导体芯片的多个区域的半导体晶片以分别分开该区域的切割线插入矩阵阵列中。 半导体晶片包括：多个测试焊盘，设置在设置在半导体芯片之间的半导体晶片的区域中，包括切割线; 与设置在所述半导体芯片之间的半导体晶片的区域中的测试焊盘平行设置的测试间互连（inter-test pad interconnect）; 所述测试间互连连接到所述测试焊盘; 以及将设计成半导体芯片的区域中的至少两个互连的芯片间互连; 所述测试间互连件电连接到所述芯片间互连。

    Semiconductor Device, Wiring Board, And Manufacturing Method Thereof
    2.
    发明申请
    Semiconductor Device, Wiring Board, And Manufacturing Method Thereof 有权
    半导体器件，接线板及其制造方法

    公开(公告)号：US20080001309A1

    公开(公告)日：2008-01-03

    申请号：US11569423

    申请日：2005-05-18

    申请人： Masamoto Tago

    发明人： Masamoto Tago

    IPC分类号： H01L23/12 ,  H05K1/00 ,  H05K3/10

    CPC分类号： H01L23/49833 ,  H01L21/4857 ,  H01L23/147 ,  H01L23/49822 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/642 ,  H01L25/162 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19105 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

    摘要： A wiring board (20) includes a first wiring portion (10) having a plurality of wiring layers (1) and a plurality of external connecting bumps (5), and a second wiring portion (15) integrated with the first wiring portion in the direction of thickness. The thermal expansion coefficient of the second wiring portion is made smaller than that of the first wiring portion, and equal to that of a semiconductor chip (30) to be mounted on the wiring board. This suppresses the internal stress resulting from the thermal expansion coefficient difference between the semiconductor chip and wiring board, and increases the reliability of a semiconductor device (50) obtained by mounting the semiconductor chip on the wiring board. The sizes of the opposing surfaces of the first and second wiring portions are also made equal. This requires only one second wiring portion to be formed even when improving the performance of the semiconductor device by mounting a plurality of semiconductor chips on the wiring board, thereby improving the performance at a low cost.

    摘要翻译： 布线基板（20）包括具有多个布线层（1）和多个外部连接凸块（5）的第一布线部分（10）和与第一布线部分 厚度方向。 使第二配线部的热膨胀系数比第一配线部的热膨胀系数小，并且等于安装在配线基板上的半导体芯片30的热膨胀系数。 这抑制了由半导体芯片和布线板之间的热膨胀系数差导致的内部应力，并且增加了将半导体芯片安装在布线板上获得的半导体器件（50）的可靠性。 第一和第二布线部分的相对表面的尺寸也相等。 即使通过将多个半导体芯片安装在布线板上来提高半导体器件的性能，也仅需要形成一个第二布线部，从而以低成本提高性能。

    Semiconductor inspecting device and semiconductor inspecting method
    8.
    发明授权
    Semiconductor inspecting device and semiconductor inspecting method 失效
    半导体检测装置及半导体检查方法

    公开(公告)号：US08536890B2

    公开(公告)日：2013-09-17

    申请号：US12865201

    申请日：2009-02-05

    申请人： Yoshio Kameda ,  Masamoto Tago ,  Yoshihiro Nakagawa ,  Koichiro Noguchi

    发明人： Yoshio Kameda ,  Masamoto Tago ,  Yoshihiro Nakagawa ,  Koichiro Noguchi

    IPC分类号： G01R31/20

    CPC分类号： G01R31/303 ,  G01R31/2889 ,  G01R31/3025

    摘要： A semiconductor inspecting device comprises a probe card for transmitting a signal or power supply to semiconductor wafers having one or more subject chips formed therein, and is constituted such that the first semiconductor wafer faces the first face of the probe card and such that the second semiconductor wafer faces the second face of the probe card on the opposite side of the first face. The probe card includes one or more inspecting chips, which can perform non-contact transmissions with the first subject chip in the first semiconductor wafer and the second subject chip in the second semiconductor wafer.

    摘要翻译： 半导体检查装置包括用于向其中形成有一个或多个对象芯片的半导体晶片发送信号或电源的探针卡，并且构成为使得第一半导体晶片面向探针卡的第一面，并且使得第二半导体 晶片面对第一面的相对侧的探针卡的第二面。 探针卡包括一个或多个检查芯片，其可以执行与第一半导体晶片中的第一对象芯片和第二半导体晶片中的第二对象芯片的非接触传输。