公开(公告)号：US06583514B2

公开(公告)日：2003-06-24

申请号：US09969657

申请日：2001-10-04

申请人： Masamoto Tago ,  Yoshihiro Tomita ,  Kenji Takahashi

发明人： Masamoto Tago ,  Yoshihiro Tomita ,  Kenji Takahashi

IPC分类号： H01L2348

CPC分类号： H01L24/13 ,  H01L23/481 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05609 ,  H01L2224/05616 ,  H01L2224/05647 ,  H01L2224/1134 ,  H01L2224/13009 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/1312 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1357 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/1362 ,  H01L2224/13664 ,  H01L2224/45144 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/8181 ,  H01L2224/8182 ,  H01L2224/81825 ,  H01L2224/8183 ,  H01L2224/81907 ,  H01L2224/8383 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/05611 ,  H01L2224/05144 ,  H01L2224/05155

摘要： A semiconductor device includes a semiconductor chip. A substrate is arranged in opposition to the semiconductor chip. A first electrode is placed on the semiconductor chip while a second electrode is placed on the substrate. Each of the first and second electrodes is made of the same electrode material. An intermetallic compound layer is formed between the first electrode and the second electrode. The intermetallic compound layer is entirely a binary alloy of the electrode material and a bonding material that was applied to at least one of the first and second electrodes.

摘要翻译： 半导体器件包括半导体芯片。 衬底被布置成与半导体芯片相对。 将第一电极放置在半导体芯片上，同时将第二电极放置在基板上。 第一和第二电极中的每一个由相同的电极材料制成。 在第一电极和第二电极之间形成金属间化合物层。 金属间化合物层完全是电极材料和施加到第一和第二电极中的至少一个的接合材料的二元合金。

公开(公告)号：US06803253B2

公开(公告)日：2004-10-12

申请号：US10000020

申请日：2001-12-04

申请人： Masamoto Tago ,  Yoshihiro Tomita

发明人： Masamoto Tago ,  Yoshihiro Tomita

IPC分类号： H01L2144

CPC分类号： H01L25/50 ,  H01L21/76898 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/81907 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/00

摘要： A plurality of semiconductor chips each having an electrode surface are sequentially laminated and mounted. Initially, the electrode surfaces of the semiconductor chips are activated. Then, the semiconductor chips are positioned. Successively, the semiconductor chips are laminated and bonded by pressing such that a reaction layer is not formed or formation of the reaction layer is suppressed excessively. Finally, the semiconductor chips are entirely heated so as to form the reaction layer after lamination and bonding of all the semiconductor chips are completed.

摘要翻译： 依次层叠并安装多个具有电极表面的半导体芯片。 最初，半导体芯片的电极表面被激活。 然后，定位半导体芯片。 接着，通过压制将半导体芯片层压并结合，使得不形成反应层或过度抑制反应层的形成。 最后，半导体芯片被完全加热，以便在层压之后形成反应层，并且完成所有半导体芯片的结合。

公开(公告)号：US20190099776A1

公开(公告)日：2019-04-04

申请号：US15720497

申请日：2017-09-29

申请人： Ken P. Hackenberg ,  Nachiket R. Raravikar ,  James C. Matayabas, JR. ,  Elizabeth Nofen ,  Nisha Ananthakrishnan ,  Manabu Nakagawasai ,  Yoshihiro Tomita

发明人： Ken P. Hackenberg ,  Nachiket R. Raravikar ,  James C. Matayabas, JR. ,  Elizabeth Nofen ,  Nisha Ananthakrishnan ,  Manabu Nakagawasai ,  Yoshihiro Tomita

IPC分类号： B05C5/02 ,  F16K21/18 ,  B05B1/02 ,  B05B1/30

摘要： A fluid applicator configured to apply a fluid to at least one substrate feature. The includes compressible reticulated media including an input interface configured for coupling with a fluid reservoir, and a substrate interface having an applicator profile corresponding to a feature profile of the at least one substrate feature. Reticulations extend from the input interface to the substrate interface, and the reticulations are distributed across the applicator profile. The compressible reticulated media includes filling and dispensing configurations. In the dispensing configuration the substrate interface is configured for engagement with the at least one substrate feature, the compressible reticulated media is compressed, and according to the compression the fluid is applied across the feature profile. In the filling configuration the compressible reticulated media is configured for expansion relative to the dispensing configuration, and the fluid infiltrates the reticulations according to the expansion.

公开(公告)号：US20150270169A1

公开(公告)日：2015-09-24

申请号：US14219749

申请日：2014-03-19

申请人： Chia-Pin Chiu ,  Kinya Ichikawa ,  Yoshihiro Tomita ,  Robert L. Sankman ,  Eric Li

发明人： Chia-Pin Chiu ,  Kinya Ichikawa ,  Yoshihiro Tomita ,  Robert L. Sankman ,  Eric Li

IPC分类号： H01L21/768 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L25/50 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/11 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/81801 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/01029 ,  H01L2924/06 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/1815 ,  H01L2924/381

摘要： A method of fabricating an electronic package. The method includes filling a mold with an electric conductor to form a number of electrical interconnects within the mold. The mold includes openings that are filled with several electric conductors to form a number of electrical interconnects. The method of fabricating an electronic package further includes attaching the mold to a substrate such that the electrical interconnects engage electrical contacts on the substrate. The method of fabricating an electronic package may further include forming conductive pads on the electrical insulator that engage the electrical interconnects and attaching a die to the substrate such that the die is electrically connected to at least some of the electrical interconnects.

摘要翻译： 一种制造电子封装的方法。 该方法包括用电导体填充模具以在模具内形成多个电互连。 模具包括填充有多个电导体以形成多个电互连的开口。 制造电子封装的方法还包括将模具附接到基板，使得电互连件接合基板上的电触点。 制造电子封装的方法还可以包括在电绝缘体上形成接合电互连并将管芯连接到衬底上的导电焊盘，使得管芯电连接到至少一些电互连。

公开(公告)号：US20130122656A1

公开(公告)日：2013-05-16

申请号：US13734861

申请日：2013-01-04

申请人： Yoshihiro Tomita ,  David Chau ,  Gregory M. Chrysler ,  Devendra Natekar

发明人： Yoshihiro Tomita ,  David Chau ,  Gregory M. Chrysler ,  Devendra Natekar

IPC分类号： H01L21/768

CPC分类号： H01L21/4867 ,  H01L21/563 ,  H01L23/3675 ,  H01L23/42 ,  H01L23/5389 ,  H01L24/24 ,  H01L2223/6677 ,  H01L2224/16225 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/351 ,  H01L2924/00

摘要： An embodiment of the present invention is a technique to fabricate a metal interconnect. A first metal trace is printed on a die attached to a substrate or a cavity of a heat spreader in a package to electrically connect the first metal trace to a power contact in the substrate. A device is mounted on the first metal trace. The device receives power from the substrate when the package is powered.

摘要翻译： 本发明的一个实施例是制造金属互连的技术。 将第一金属迹线印刷在附接到封装中的散热器的基板或空腔的管芯上，以将第一金属迹线电连接到基板中的电源触点。 设备安装在第一个金属轨迹上。 当封装电源时，该设备从基板接收电力。

公开(公告)号：US08387240B2

公开(公告)日：2013-03-05

申请号：US12955816

申请日：2010-11-29

申请人： Sriram Muthukumar ,  Raul Mancera ,  Yoshihiro Tomita ,  Chi-won Hwang

发明人： Sriram Muthukumar ,  Raul Mancera ,  Yoshihiro Tomita ,  Chi-won Hwang

IPC分类号： H01K3/10

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L23/147 ,  H01L25/0655 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2924/10253 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49163 ,  Y10T29/49165 ,  H01L2924/00

摘要： In one embodiment, a method includes forming a plurality of vias partially through a body, the vias including sidewalls defined by the body. An electrically insulating layer is formed on the sidewalls and on an upper surface of the body. An electrically conductive layer is formed on the insulating layer in the vias and on the upper surface, the electrically conductive layer defining first metal pads on the upper surface and second metal pads in contact with the first metal pads, the second metal pads having a denser pitch than the first metal pads. A dielectric layer is formed between adjacent first metal pads and between adjacent second metal pads. The body is thinned through a lower surface and the electrically insulating layer in the vias is exposed. After the thinning, a portion of the electrically insulating layer in the, vias is removed. The body is coupled to a substrate.

摘要翻译： 在一个实施例中，一种方法包括通过主体部分地形成多个通孔，通孔包括由身体限定的侧壁。 电绝缘层形成在主体的侧壁和上表面上。 在通孔和上表面上的绝缘层上形成导电层，导电层限定上表面上的第一金属焊盘和与第一金属焊盘接触的第二金属焊盘，第二金属焊盘具有较密的 间距比第一金属垫。 在相邻的第一金属焊盘之间和相邻的第二金属焊盘之间形成介电层。 身体通过下表面变薄，并且通孔中的电绝缘层被暴露。 在变薄之后，去除通孔中的电绝缘层的一部分。 主体耦合到基板。

公开(公告)号：US08354748B2

公开(公告)日：2013-01-15

申请号：US13354708

申请日：2012-01-20

申请人： Sriram Dattaguru ,  Lesley A. Polka Wood ,  Yoshihiro Tomita ,  Kiniya Ichikawa ,  Robert L. Sankman

发明人： Sriram Dattaguru ,  Lesley A. Polka Wood ,  Yoshihiro Tomita ,  Kiniya Ichikawa ,  Robert L. Sankman

IPC分类号： H01L23/34 ,  H01L21/00 ,  H05K1/18

CPC分类号： H01L25/0657 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/48 ,  H01L24/82 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/06517 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01065 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A mounting substrate for a processor includes a die side and a land side with a processor footprint configured on the die side. The processor footprint is coupled to at least one processor interconnect and a microelectronic die is embedded in the mounting substrate. The microelectronic die is coupled to the processor interconnect and communication between a processor to be installed on the processor footprint is in a rate between 10 Gb/s and 1 Tb/s.

摘要翻译： 用于处理器的安装基板包括裸片侧和在裸片侧配置有处理器占位面的平台侧。 处理器占用面积耦合到至少一个处理器互连，并且微电子管芯嵌入在安装衬底中。 微电子管芯耦合到处理器互连，并且待处理器占用的处理器之间的通信速率在10Gb / s至1Tb / s之间。

公开(公告)号：US20120289002A1

公开(公告)日：2012-11-15

申请号：US13556079

申请日：2012-07-23

申请人： Yoshihiro Tomita ,  David Chau ,  Gregory M. Chrysler ,  Devendra Natekar

发明人： Yoshihiro Tomita ,  David Chau ,  Gregory M. Chrysler ,  Devendra Natekar

IPC分类号： H01L21/50

CPC分类号： H01L21/4867 ,  H01L21/563 ,  H01L23/3675 ,  H01L23/42 ,  H01L23/5389 ,  H01L24/24 ,  H01L2223/6677 ,  H01L2224/16225 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/351 ,  H01L2924/00

摘要： An embodiment of the present invention is a technique to fabricate a metal interconnect. A first metal trace is printed on a die attached to a substrate or a cavity of a heat spreader in a package to electrically connect the first metal trace to a power contact in the substrate. A device is mounted on the first metal trace. The device receives power from the substrate when the package is powered.

摘要翻译： 本发明的一个实施例是制造金属互连的技术。 将第一金属迹线印刷在附接到封装中的散热器的基板或空腔的管芯上，以将第一金属迹线电连接到基板中的电源触点。 设备安装在第一个金属轨迹上。 当封装电源时，该设备从基板接收电力。

公开(公告)号：US20120038033A1

公开(公告)日：2012-02-16

申请号：US13285896

申请日：2011-10-31

申请人： Akira OGA ,  Yoshihiro Tomita ,  Masanori Minamio

发明人： Akira OGA ,  Yoshihiro Tomita ,  Masanori Minamio

IPC分类号： H01L23/495

CPC分类号： H01L21/565 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/552 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45147 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2924/206

摘要： A semiconductor device includes a first semiconductor chip 1, a second semiconductor chip 4, a first lead frame 3 including a first die pad 9 on which the first semiconductor chip 1 is mounted, and a second lead frame 5 including a second die pad 11 on which the second semiconductor chip 4 is mounted. A sealing structure 6 covers the first semiconductor chip 1 and the second semiconductor chip 4. A noise shield 7 is disposed between the first semiconductor chip 1 and the second semiconductor chip 4.

摘要翻译： 半导体器件包括第一半导体芯片1，第二半导体芯片4，第一引线框架3，第一引线框架3和第二引线框架3，第一引线框架3包括安装有第一半导体芯片1的第一管芯焊盘9和第二引线框架5， 第二半导体芯片4被安装。 密封结构6覆盖第一半导体芯片1和第二半导体芯片4.噪声屏蔽7设置在第一半导体芯片1和第二半导体芯片4之间。

公开(公告)号：US20110147905A1

公开(公告)日：2011-06-23

申请号：US13039937

申请日：2011-03-03

申请人： Masaki Utsumi ,  Hikari Sano ,  Hiroaki Fujimoto ,  Yoshihiro Tomita

发明人： Masaki Utsumi ,  Hikari Sano ,  Hiroaki Fujimoto ,  Yoshihiro Tomita

IPC分类号： H01L23/06 ,  H01L21/78

CPC分类号： H01L33/62 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/14618 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01055 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： In a semiconductor element, upper through-hole conductor portions and lower through-hole conductor portions are formed such that pore size A of the joint surface of the upper through-hole conductor portion and the lower through-hole conductor portion is smaller than pore size B of the upper through-hole conductor portion on the major surface of the semiconductor element and pore size C of the lower through-hole conductor portion on the other surface of the semiconductor element. Further, electrode portions are formed respectively on the top surfaces of the upper through-hole conductor portions and protrusions 4 are formed respectively on the top surfaces of the electrode portions. Moreover, an optical member pressed in contact with the protrusions is fixed on the semiconductor element with an adhesive.

摘要翻译： 在半导体元件中，形成上通孔导体部和下通孔导体部，使得上通孔导体部和下通孔导体部的接合面的孔径A小于孔径 B，半导体元件的主表面上的上通孔导体部分的孔径C和半导体元件另一表面上的下通孔导体部分的孔径C. 此外，电极部分分别形成在上通孔导体部分的顶表面上，突起4分别形成在电极部分的顶表面上。 此外，用粘合剂固定在半导体元件上与突起接触的光学部件。