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110 条记录 (耗时 0.033 秒)

    EXTENDING MULTICHIP PACKAGE LINK OFF PACKAGE
    2.
    发明申请
    EXTENDING MULTICHIP PACKAGE LINK OFF PACKAGE 有权

    公开(公告)号：US20210097015A1

    公开(公告)日：2021-04-01

    申请号：US17121534

    申请日：2020-12-14

    申请人： Intel Corporation

    发明人： Debendra Das Sharma ,  Zuoguo Wu ,  Mahesh Wagh ,  Mohiuddin M. Mazumder ,  Venkatraman Iyer ,  Jeff C. Morriss

    IPC分类号： G06F13/40 ,  H01L23/538 ,  H01L25/065 ,  G06F13/42

    摘要： An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.

    FLEX BUS PROTOCOL NEGOTIATION AND ENABLING SEQUENCE
    4.
    发明申请
    FLEX BUS PROTOCOL NEGOTIATION AND ENABLING SEQUENCE 审中-公开

    公开(公告)号：US20200210366A1

    公开(公告)日：2020-07-02

    申请号：US16812156

    申请日：2020-03-06

    申请人： Intel Corporation

    发明人： Debendra Das Sharma ,  Michelle C. Jen ,  Prahladachar Jayaprakash Bharadwaj ,  Bruce A. Tennant ,  Mahesh Wagh

    IPC分类号： G06F13/40 ,  G06F13/42

    摘要： Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.

    Multichip package link error detection
    5.
    发明授权
    Multichip package link error detection 有权

    公开(公告)号：US10552253B2

    公开(公告)日：2020-02-04

    申请号：US15741967

    申请日：2015-09-26

    申请人： INTEL CORPORATION

    发明人： Venkatraman Iyer ,  Robert G. Blankenship ,  Mahesh Wagh ,  Zuoguo Wu

    IPC分类号： G06F11/10 ,  H03M13/00 ,  G06F13/16

    摘要： First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.

    Link-physical layer interface adapter
    6.
    发明授权
    Link-physical layer interface adapter 有权

    公开(公告)号：US10152446B2

    公开(公告)日：2018-12-11

    申请号：US15283309

    申请日：2016-10-01

    申请人： Intel Corporation

    发明人： Venkatraman Iyer ,  Mahesh Wagh ,  William R. Halleck ,  Rahul R. Shah

    IPC分类号： G06F13/38 ,  G06F13/36 ,  G06F13/40 ,  G06F13/42 ,  G11C27/04

    摘要： An interface adapter to identify a first ready signal from a first link layer-to-physical layer (LL-PHY) interface of a first communication protocol indicating readiness of a physical layer of the first protocol to accept link layer data. The interface adapter generates a second ready signal compatible with a second LL-PHY interface of a second communication protocol to cause link layer data to be sent from a link layer of the second communication protocol according to a predefined delay. A third ready signal is generated compatible with the first LL-PHY interface to indicate to the physical layer of the first communication protocol that the link layer data is to be sent. The interface adapter uses a shift register to cause the link layer data to be passed to the physical layer according to the predefined delay.

    Method, apparatus, and system for improving resume times for root ports and root port integrated endpoints
    7.
    发明授权
    Method, apparatus, and system for improving resume times for root ports and root port integrated endpoints 有权

    公开(公告)号：US10139889B2

    公开(公告)日：2018-11-27

    申请号：US14998158

    申请日：2015-12-24

    申请人： Intel Corporation

    发明人： Mahesh Wagh ,  Robert E. Gough

    IPC分类号： G06F1/32 ,  G06F13/42 ,  G06F9/44 ,  H04L12/933 ,  G06F9/4401

    摘要： A system on a chip (SoC) is provided with a multicore processor, a level-2 (L2) cache controller, an L2 cache, an integrated memory controller, and a serial point-to-point link interface to enable communication between the multicore processor and a device. The interface implements a protocol stack and includes a transmitter to transmit serial data to the device and a receiver to deserialize an incoming serial stream. The protocol stack supports a plurality of power management states, including an active state, a first off state, in which a supply voltage is to be provided to the device, and a second off state, in which the supply voltage is not to be provided to the device. In response to an indication the device is ready to enter the active state, the protocol stack provides for accessing the device prior to expiration of a default recovery time to complete the transition.