公开(公告)号：US20170294906A1

公开(公告)日：2017-10-12

申请号：US15632836

申请日：2017-06-26

申请人： Intel Corporation

发明人： Mahesh Wagh ,  Zuoguo J. Wu ,  Venkatraman Iyer ,  Gerald S. Pasdast ,  Todd A. Hinck ,  David M. Lee ,  Narasimha R. Lanka

IPC分类号： H03K5/26 ,  G06F1/32 ,  G06F13/42 ,  H03L9/00 ,  G01R31/04

CPC分类号： H03K5/26 ,  G01R31/041 ,  G06F1/3296 ,  G06F13/4291 ,  H03K5/131 ,  H03L9/00

摘要： In an example, a system and method for centering in a high-performance interconnect (HPI) are disclosed. When an interconnect is powered up from a dormant state, it may be necessary to “center” the clock signal to ensure that data are read at the correct time. A multi-phase method may be used, in which a first phase comprises a reference voltage sweep to identify an optimal reference voltage. A second phase comprises a phase sweep to identify an optimal phase. A third sweep comprises a two-dimensional “eye” phase, in which a plurality of values within a two-dimensional eye derived from the first two sweeps are tested. In each case, the optimal value is the value that results in the fewest bit error across multiple lanes. In one example, the second and third phases are performed in software, and may include testing a “victim” lane, with adjacent “aggressor” lanes having a complementary bit pattern.

公开(公告)号：US10552357B2

公开(公告)日：2020-02-04

申请号：US15821492

申请日：2017-11-22

申请人： Intel Corporation

发明人： Zuoguo J. Wu ,  Mahesh Wagh ,  Debendra Das Sharma ,  Gerald S. Pasdast ,  Ananthan Ayyasamy ,  Xiaobei Li ,  Robert G. Blankenship ,  Robert J. Safranek

IPC分类号： G06F13/40 ,  G06F13/42 ,  G06F13/12 ,  G06F15/173 ,  G06F1/10

摘要： Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.

公开(公告)号：US10073808B2

公开(公告)日：2018-09-11

申请号：US15039452

申请日：2013-12-26

申请人： Intel Corporation

发明人： Zuoguo J. Wu ,  Mahesh Wagh ,  Debendra Das Sharma ,  Gerald S. Pasdast ,  Ananthan Ayyasamy ,  Xiaobei Li ,  Robert G. Blankenship ,  Robert J. Safranek

IPC分类号： G06F13/00 ,  G06F13/42 ,  G06F13/12 ,  G06F15/173

CPC分类号： G06F13/4022 ,  G06F1/10 ,  G06F13/124 ,  G06F13/4273 ,  G06F13/4282 ,  G06F15/173 ,  Y02D10/14 ,  Y02D10/151

摘要： Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.

公开(公告)号：US20170083475A1

公开(公告)日：2017-03-23

申请号：US15039452

申请日：2013-12-26

申请人： Intel Corporation

发明人： Zuoguo J. Wu ,  Mahesh Wagh ,  Debendra Das Sharma ,  Gerald S. Pasdast ,  Ananthan Ayyasamy ,  Xiaobei Li ,  Robert G. Blankenship ,  Robert J. Safranek

IPC分类号： G06F13/42 ,  G06F15/173 ,  G06F13/12

CPC分类号： G06F13/4282 ,  G06F13/124 ,  G06F13/4273 ,  G06F15/173 ,  Y02D10/14 ,  Y02D10/151

摘要： Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.

公开(公告)号：US10560081B2

公开(公告)日：2020-02-11

申请号：US15632836

申请日：2017-06-26

申请人： Intel Corporation

发明人： Mahesh Wagh ,  Zuoguo J. Wu ,  Venkatraman Iyer ,  Gerald S. Pasdast ,  Todd A. Hinck ,  David M. Lee ,  Narasimha R. Lanka

IPC分类号： H03K5/26 ,  G01R31/04 ,  H03L9/00 ,  G06F1/3296 ,  G06F13/42 ,  H03K5/131

摘要： In an example, a system and method for centering in a high-performance interconnect (HPI) are disclosed. When an interconnect is powered up from a dormant state, it may be necessary to “center” the clock signal to ensure that data are read at the correct time. A multi-phase method may be used, in which a first phase comprises a reference voltage sweep to identify an optimal reference voltage. A second phase comprises a phase sweep to identify an optimal phase. A third sweep comprises a two-dimensional “eye” phase, in which a plurality of values within a two-dimensional eye derived from the first two sweeps are tested. In each case, the optimal value is the value that results in the fewest bit error across multiple lanes. In one example, the second and third phases are performed in software, and may include testing a “victim” lane, with adjacent “aggressor” lanes having a complementary bit pattern.

公开(公告)号：US20180300275A1

公开(公告)日：2018-10-18

申请号：US15821492

申请日：2017-11-22

申请人： Intel Corporation

发明人： Zuoguo J. Wu ,  Mahesh Wagh ,  Debendra Das Sharma ,  Gerald S. Pasdast ,  Ananthan Ayyasamy ,  Xiaobei Li ,  Robert G. Blankenship ,  Robert J. Safranek

IPC分类号： G06F13/40 ,  G06F1/10

CPC分类号： G06F13/4022 ,  G06F1/10 ,  G06F13/124 ,  G06F13/4273 ,  G06F13/4282 ,  G06F15/173 ,  Y02D10/14 ,  Y02D10/151

摘要： Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.