Invention Grant
- Patent Title: Multichip package link
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Application No.: US15821492Application Date: 2017-11-22
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Publication No.: US10552357B2Publication Date: 2020-02-04
- Inventor: Zuoguo J. Wu , Mahesh Wagh , Debendra Das Sharma , Gerald S. Pasdast , Ananthan Ayyasamy , Xiaobei Li , Robert G. Blankenship , Robert J. Safranek
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Alliance IP, LLC
- Main IPC: G06F13/40
- IPC: G06F13/40 ; G06F13/42 ; G06F13/12 ; G06F15/173 ; G06F1/10

Abstract:
Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.
Public/Granted literature
- US20180300275A1 MULTICHIP PACKAGE LINK Public/Granted day:2018-10-18
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