公开(公告)号：US11726939B2

公开(公告)日：2023-08-15

申请号：US17485337

申请日：2021-09-25

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Prahladachar Jayaprakash Bharadwaj ,  Bruce Tennant ,  Mahesh Wagh

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4027 ,  G06F13/4282 ,  G06F2213/0026

Abstract: Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.

公开(公告)号：US20210097015A1

公开(公告)日：2021-04-01

申请号：US17121534

申请日：2020-12-14

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Zuoguo Wu ,  Mahesh Wagh ,  Mohiuddin M. Mazumder ,  Venkatraman Iyer ,  Jeff C. Morriss

IPC: G06F13/40 ,  H01L23/538 ,  H01L25/065 ,  G06F13/42

Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.

公开(公告)号：US10884195B2

公开(公告)日：2021-01-05

申请号：US15396501

申请日：2016-12-31

Applicant: INTEL CORPORATION

Inventor： Mahesh Wagh ,  Mark S. Myers ,  Stephen R. Van Doren ,  Dimitrios Ziakas ,  Bassam Coury

IPC: H03M7/40 ,  G02B6/38 ,  G02B6/42 ,  G02B6/44 ,  G06F16/901 ,  H04B10/25 ,  G06F3/06 ,  G11C5/02 ,  G11C14/00 ,  H04L12/24 ,  H04L12/26 ,  H04Q11/00 ,  G06F1/20 ,  H04W4/80 ,  G06F1/18 ,  G06F8/65 ,  G06F9/30 ,  G06F9/38 ,  G06F9/4401 ,  G06F9/50 ,  G06F9/54 ,  G06F12/109 ,  G06F12/14 ,  G06F13/16 ,  G06F13/40 ,  G06Q10/08 ,  G06Q10/00 ,  G06Q50/04 ,  G08C17/02 ,  G11C7/10 ,  G11C11/56 ,  H03M7/30 ,  H04L12/851 ,  H04L12/811 ,  H04L12/931 ,  H04L29/08 ,  H04L29/06 ,  H05K5/02 ,  H05K7/14 ,  H04L12/911 ,  B25J15/00 ,  B65G1/04 ,  H05K7/20 ,  H04L12/939 ,  H04W4/02 ,  H04L12/751 ,  G06F13/42 ,  H05K1/18 ,  G05D23/19 ,  G05D23/20 ,  H04L12/927 ,  H05K1/02 ,  H04L12/781 ,  H04Q1/04 ,  G06F12/0893 ,  H05K13/04 ,  G11C5/06 ,  G06F11/14 ,  G06F11/34 ,  G06F12/0862 ,  G06F15/80 ,  H04L12/919 ,  G06F12/10 ,  G06Q10/06 ,  G07C5/00 ,  H04L12/28 ,  H04L29/12 ,  H04L9/06 ,  H04L9/14 ,  H04L9/32 ,  H04L12/933 ,  H04L12/947

Abstract: Embodiments may be generally direct to apparatuses, systems, method, and techniques to determine a configuration for a plurality of connectors, the configuration to associate a first interconnect protocol with a first subset of the plurality of connectors and a second interconnect protocol with a second subset of the plurality of connectors, the first interconnect protocol and the second interconnect protocol are different interconnect protocols and each comprising one of a serial link protocol, a coherent link protocol, and an accelerator link protocol, cause processing of data for communication via the first subset of the plurality of connectors in accordance with the first interconnect protocol, and cause processing of data for communication via the second subset of the plurality of connector in accordance with the second interconnect protocol.

公开(公告)号：US20200210366A1

公开(公告)日：2020-07-02

申请号：US16812156

申请日：2020-03-06

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Prahladachar Jayaprakash Bharadwaj ,  Bruce A. Tennant ,  Mahesh Wagh

IPC: G06F13/40 ,  G06F13/42

Abstract: Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.

公开(公告)号：US10552253B2

公开(公告)日：2020-02-04

申请号：US15741967

申请日：2015-09-26

Applicant: INTEL CORPORATION

Inventor： Venkatraman Iyer ,  Robert G. Blankenship ,  Mahesh Wagh ,  Zuoguo Wu

IPC: G06F11/10 ,  H03M13/00 ,  G06F13/16

Abstract: First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.

公开(公告)号：US10152446B2

公开(公告)日：2018-12-11

申请号：US15283309

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Venkatraman Iyer ,  Mahesh Wagh ,  William R. Halleck ,  Rahul R. Shah

IPC: G06F13/38 ,  G06F13/36 ,  G06F13/40 ,  G06F13/42 ,  G11C27/04

Abstract: An interface adapter to identify a first ready signal from a first link layer-to-physical layer (LL-PHY) interface of a first communication protocol indicating readiness of a physical layer of the first protocol to accept link layer data. The interface adapter generates a second ready signal compatible with a second LL-PHY interface of a second communication protocol to cause link layer data to be sent from a link layer of the second communication protocol according to a predefined delay. A third ready signal is generated compatible with the first LL-PHY interface to indicate to the physical layer of the first communication protocol that the link layer data is to be sent. The interface adapter uses a shift register to cause the link layer data to be passed to the physical layer according to the predefined delay.

公开(公告)号：US10139889B2

公开(公告)日：2018-11-27

申请号：US14998158

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Mahesh Wagh ,  Robert E. Gough

IPC: G06F1/32 ,  G06F13/42 ,  G06F9/44 ,  H04L12/933 ,  G06F9/4401

Abstract: A system on a chip (SoC) is provided with a multicore processor, a level-2 (L2) cache controller, an L2 cache, an integrated memory controller, and a serial point-to-point link interface to enable communication between the multicore processor and a device. The interface implements a protocol stack and includes a transmitter to transmit serial data to the device and a receiver to deserialize an incoming serial stream. The protocol stack supports a plurality of power management states, including an active state, a first off state, in which a supply voltage is to be provided to the device, and a second off state, in which the supply voltage is not to be provided to the device. In response to an indication the device is ready to enter the active state, the protocol stack provides for accessing the device prior to expiration of a default recovery time to complete the transition.

公开(公告)号：US20180276164A1

公开(公告)日：2018-09-27

申请号：US15761401

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Zuoguo Wu ,  Mahesh Wagh ,  Mohiuddin M. Mazumder ,  Venkatraman Iyer ,  Jeff C. Morriss

IPC: G06F13/40 ,  H01L25/065 ,  H01L23/538

CPC classification number: G06F13/4027 ,  G06F13/4022 ,  G06F13/405 ,  G06F13/4265 ,  H01L23/5386 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.

公开(公告)号：US10073808B2

公开(公告)日：2018-09-11

申请号：US15039452

申请日：2013-12-26

Applicant: Intel Corporation

Inventor： Zuoguo J. Wu ,  Mahesh Wagh ,  Debendra Das Sharma ,  Gerald S. Pasdast ,  Ananthan Ayyasamy ,  Xiaobei Li ,  Robert G. Blankenship ,  Robert J. Safranek

IPC: G06F13/00 ,  G06F13/42 ,  G06F13/12 ,  G06F15/173

CPC classification number: G06F13/4022 ,  G06F1/10 ,  G06F13/124 ,  G06F13/4273 ,  G06F13/4282 ,  G06F15/173 ,  Y02D10/14 ,  Y02D10/151

Abstract: Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.

公开(公告)号：US20180196710A1

公开(公告)日：2018-07-12

申请号：US15741967

申请日：2015-09-26

Applicant: INTEL CORPORATION

Inventor： Venkatraman Iyer ,  Robert G. Blankenship ,  Mahesh Wagh ,  Zuoguo Wu

IPC: G06F11/10 ,  G06F13/16

CPC classification number: G06F11/1004 ,  G06F13/16 ,  G06F2213/16 ,  H04L1/00 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0061 ,  H04L1/0075 ,  H04L1/1607 ,  H04L1/20 ,  H04L29/06 ,  H04L2001/0094 ,  Y02D10/14

Abstract: First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.