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    BIMODAL PHY FOR LOW LATENCY IN HIGH SPEED INTERCONNECTS
    2.
    发明申请
    BIMODAL PHY FOR LOW LATENCY IN HIGH SPEED INTERCONNECTS 审中-公开

    公开(公告)号：US20200293480A1

    公开(公告)日：2020-09-17

    申请号：US16802209

    申请日：2020-02-26

    Applicant: INTEL CORPORATION

    Inventor： Venkatraman Iyer ,  William R. Halleck ,  Rahul R. Shah ,  Eric Lee

    IPC: G06F13/40 ,  G06F13/42 ,  G06F13/16 ,  G06F13/38

    Abstract: Systems, methods, and apparatuses including a Physical layer (PHY) block coupled to a Media Access Control layer (MAC) block via a PHY/MAC interface. Each of the PHY and MAC blocks include a plurality of Physical Interface for PCI Express (PIPE) registers. The PHY/MAC interface includes a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block. The MAC block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of PHY PIPE registers, and the PHY block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of MAC PIPE registers. The PHY block may also be selectively configurable to implement a PIPE architecture to operate in a PIPE mode and a serialization and deserialization (SERDES) architecture to operate in a SERDES mode.

    HIGH PERFORMANCE INTERCONNECT LINK STATE TRANSITIONS
    3.
    发明申请
    HIGH PERFORMANCE INTERCONNECT LINK STATE TRANSITIONS 有权
    高性能互连链路状态转换

    公开(公告)号：US20160179730A1

    公开(公告)日：2016-06-23

    申请号：US14578175

    申请日：2014-12-19

    Applicant: Intel Corporation

    Inventor： William R. Halleck ,  Rahul Shah ,  Venkatraman Iyer

    IPC: G06F13/40 ,  G06F13/42

    CPC classification number: G06F13/4027 ,  G06F13/124 ,  G06F13/1678 ,  G06F13/4282

    Abstract: A supersequence is sent to another device to indicate a transition from a partial width link state to another active link state. The supersequence is to be sent over one or more lanes of a link and is to include at least a portion of a start of data sequence (SDS) to include a predefined sequence and a byte number value. The byte number value is to indicate a number of bytes measured from a preceding control interval.

    Abstract translation: 将超级序列发送到另一设备以指示从部分宽度链路状态到另一活动链路状态的转换。 超级序列将通过链路的一个或多个通道发送，并且包括数据序列（SDS）的起始的至少一部分以包括预定义的序列和字节数值。 字节数值表示从前一个控制间隔测量的字节数。

    BIMODAL PHY FOR LOW LATENCY IN HIGH SPEED INTERCONNECTS
    4.
    发明申请
    BIMODAL PHY FOR LOW LATENCY IN HIGH SPEED INTERCONNECTS 审中-公开

    公开(公告)号：US20190310959A1

    公开(公告)日：2019-10-10

    申请号：US16446996

    申请日：2019-06-20

    Applicant: INTEL CORPORATION

    Inventor： Venkatraman Iyer ,  William R. Halleck ,  Rahul R. Shah ,  Eric Lee

    IPC: G06F13/40 ,  G06F13/38 ,  G06F13/16 ,  G06F13/42

    Abstract: Systems, methods, and apparatuses including a Physical layer (PHY) block coupled to a Media Access Control layer (MAC) block via a PHY/MAC interface. Each of the PHY and MAC blocks include a plurality of Physical Interface for PCI Express (PIPE) registers. The PHY/MAC interface includes a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block. The MAC block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of PHY PIPE registers, and the PHY block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of MAC PIPE registers. The PHY block may also be selectively configurable to implement a PIPE architecture to operate in a PIPE mode and a serialization and deserialization (SERDES) architecture to operate in a SERDES mode.

    Bimodal PHY for low latency in high speed interconnects
    5.
    发明授权
    Bimodal PHY for low latency in high speed interconnects 有权

    公开(公告)号：US10372657B2

    公开(公告)日：2019-08-06

    申请号：US15390648

    申请日：2016-12-26

    Applicant: Intel Corporation

    Inventor： Venkatraman Iyer ,  William R. Halleck ,  Rahul R. Shah ,  Eric Lee

    IPC: G06F13/00 ,  G06F13/40 ,  G06F13/42 ,  G06F13/16 ,  G06F13/38

    Abstract: Systems, methods, and apparatuses including a Physical layer (PHY) block coupled to a Media Access Control layer (MAC) block via a PHY/MAC interface. Each of the PHY and MAC blocks include a plurality of Physical Interface for PCI Express (PIPE) registers. The PHY/MAC interface includes a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block. The low pin count PIPE interface is configured to transfer register commands between the PHY and MAC blocks over the small set of wires in a time-multiplexed manner to support read and write access of the PHY and MAC PIPE registers. The PHY block may also be selectively configurable to implement a PIPE architecture when operating in a PIPE mode and a serialization and deserialization (SERDES) architecture when operating in a SERDES mode.

    High performance interconnect link state transitions
    6.
    发明授权
    High performance interconnect link state transitions 有权

    公开(公告)号：US10324882B2

    公开(公告)日：2019-06-18

    申请号：US15393631

    申请日：2016-12-29

    Applicant: Intel Corporation

    Inventor： William R. Halleck ,  Rahul R. Shah ,  Venkatraman Iyer

    IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  G06F13/12

    Abstract: An exit pattern is sent to initiate exit from a partial width state, where only a portion of the available lanes of a link are used to transmit data and the remaining lanes are idle. The exit pattern is sent on the idle lanes, the exit pattern including an electrical ordered set (EOS), one or more fast training sequences (FTS), a start of data sequence (SDS), and a partial fast training sequence (FTSp). The SDS includes a byte number field to indicate a number of a bytes measured from a previous control interval of the link, and an end of the SDS is sent to coincide with a clean flit boundary on the active lanes. The partial width state is exited based on the exit pattern and data is sent on all available lanes following the exit from the partial width state.

    HIGH SPEED INTERCONNECT WITH CHANNEL EXTENSION
    7.
    发明申请
    HIGH SPEED INTERCONNECT WITH CHANNEL EXTENSION 审中-公开

    公开(公告)号：US20180191523A1

    公开(公告)日：2018-07-05

    申请号：US15394278

    申请日：2016-12-29

    Applicant: Intel Corporation

    Inventor： Rahul R. Shah ,  William R. Halleck ,  Fulvio Spagna ,  Venkatraman Iyer

    IPC: H04L12/407 ,  H04L12/933 ,  H04B3/36

    CPC classification number: H04B3/36 ,  G06F13/40 ,  H04L47/125

    Abstract: An apparatus includes an agent to facilitate communication in one of two or more modes, where a first of the two or more modes involves communication over links including a first number of lanes and a second of the two or more modes involves communication over links including a second number of lanes, and the first number is greater than the second number. The apparatus further includes a memory including data to indicate which of the two or modes applies to a particular link and a multiplexer to reverse lane numbering on links including either the first number of lanes or the second number of lanes.

    Bimodal phy for low latency in high speed interconnects
    9.
    发明授权
    Bimodal phy for low latency in high speed interconnects 有权

    公开(公告)号：US10599602B2

    公开(公告)日：2020-03-24

    申请号：US16446996

    申请日：2019-06-20

    Applicant: INTEL CORPORATION

    Inventor： Venkatraman Iyer ,  William R. Halleck ,  Rahul R. Shah ,  Eric Lee

    IPC: G06F13/40 ,  G06F13/38 ,  G06F13/42 ,  G06F13/16

    Abstract: Systems, methods, and apparatuses including a Physical layer (PHY) block coupled to a Media Access Control layer (MAC) block via a PHY/MAC interface. Each of the PHY and MAC blocks include a plurality of Physical Interface for PCI Express (PIPE) registers. The PHY/MAC interface includes a low pin count PIPE interface comprising a small set of wires coupled between the PHY block and the MAC block. The MAC block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of PHY PIPE registers, and the PHY block is configured to multiplex command, address, and data over the low pin count PIPE interface to access the plurality of MAC PIPE registers. The PHY block may also be selectively configurable to implement a PIPE architecture to operate in a PIPE mode and a serialization and deserialization (SERDES) architecture to operate in a SERDES mode.

    BIMODAL PHY FOR LOW LATENCY IN HIGH SPEED INTERCONNECTS
    10.
    发明申请
    BIMODAL PHY FOR LOW LATENCY IN HIGH SPEED INTERCONNECTS 审中-公开

    公开(公告)号：US20180181525A1

    公开(公告)日：2018-06-28

    申请号：US15390648

    申请日：2016-12-26

    Applicant: Intel Corporation

    Inventor： Venkatraman Iyer ,  William R. Halleck ,  Rahul R. Shah ,  Eric Lee

    IPC: G06F13/40 ,  G06F13/42 ,  G06F13/16

    CPC classification number: G06F13/4068 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/382 ,  G06F13/385 ,  G06F13/4282 ,  G06F2213/0026

    Abstract: Systems, methods, and apparatuses involve a PHY coupled to a MAC. The PHY can include a drift buffer coupled to an output of a receiver and a bypass branch coupled to the output of the receiver. The PHY includes a clocking multiplexer that includes a first clock input coupled to a recovered clock of the PHY and a second clock input coupled to a p-clock of the MAC; and a clock output configured to output one of the recovered clock or the p-clock based on a selection input value. The PHY includes a bypass multiplexer that includes a first data input coupled to an output of a drift buffer and a second data input coupled to the bypass branch; and a data output configured to output one of the output of the drift buffer or data from the bypass branch based on the section input value of the clocking multiplexer.

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