Invention Application
- Patent Title: BIMODAL PHY FOR LOW LATENCY IN HIGH SPEED INTERCONNECTS
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Application No.: US15390648Application Date: 2016-12-26
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Publication No.: US20180181525A1Publication Date: 2018-06-28
- Inventor: Venkatraman Iyer , William R. Halleck , Rahul R. Shah , Eric Lee
- Applicant: Intel Corporation
- Main IPC: G06F13/40
- IPC: G06F13/40 ; G06F13/42 ; G06F13/16

Abstract:
Systems, methods, and apparatuses involve a PHY coupled to a MAC. The PHY can include a drift buffer coupled to an output of a receiver and a bypass branch coupled to the output of the receiver. The PHY includes a clocking multiplexer that includes a first clock input coupled to a recovered clock of the PHY and a second clock input coupled to a p-clock of the MAC; and a clock output configured to output one of the recovered clock or the p-clock based on a selection input value. The PHY includes a bypass multiplexer that includes a first data input coupled to an output of a drift buffer and a second data input coupled to the bypass branch; and a data output configured to output one of the output of the drift buffer or data from the bypass branch based on the section input value of the clocking multiplexer.
Public/Granted literature
- US10372657B2 Bimodal PHY for low latency in high speed interconnects Public/Granted day:2019-08-06
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