公开(公告)号：US20160335148A1

公开(公告)日：2016-11-17

申请号：US15042463

申请日：2016-02-12

Applicant: Intel Corporation

Inventor： Prahladachar Jayaprakash Bharadwaj ,  Alexander Brown ,  Debendra Das Sharma ,  Junaid Thaliyil

IPC: G06F11/07

CPC classification number: G06F11/0745 ,  G06F11/0736 ,  G06F11/0793 ,  G06F11/1415 ,  G06F11/1443

Abstract: A packet is identified at a port of a serial data link, and it is determined that the packet is associated with an error. Entry into an error recovery mode is initiated based on the determination that the packet is associated with the error. Entry into the error recovery mode can cause the serial data link to be forced down. In one aspect, forcing the data link down causes all subsequent inbound packets to be dropped and all pending outbound requests and completions to be aborted during the error recovery mode.

Abstract translation: 在串行数据链路的端口处识别分组，并且确定分组与错误相关联。 基于确定该分组与该错误相关联来进入错误恢复模式。 进入错误恢复模式可能导致串行数据链路被强制关闭。 在一个方面，强制数据链路断开导致所有后续入站分组被丢弃，并且所有待处理的出站请求和完成将在错误恢复模式期间中止。

公开(公告)号：US11669481B2

公开(公告)日：2023-06-06

申请号：US17559002

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Michelle Jen ,  Debendra Das Sharma ,  Bruce Tennant ,  Prahladachar Jayaprakash Bharadwaj

IPC: G06F13/40 ,  H04L69/16 ,  G06F1/3237 ,  G06F13/42 ,  G06F13/38

CPC classification number: G06F13/4068 ,  G06F1/3237 ,  G06F13/4291 ,  H04L69/161 ,  G06F13/385

Abstract: Methods and apparatuses associated with a secure stream protocol for a serial interconnect are disclosed herein. In embodiments, an apparatus comprises a transmitter and a receiver. The transmitter and receiver are configured to transmit and receive transaction layer data packets through a link, the transaction layer data packets including indicators associated with transmission of order set transmitted after a predetermined number of data blocks, when the transmission is during a header suppression mode. Additional features and other embodiments are also disclosed.

公开(公告)号：US09454213B2

公开(公告)日：2016-09-27

申请号：US14141184

申请日：2013-12-26

Applicant: Intel Corporation

Inventor： Prahladachar Jayaprakash Bharadwaj ,  Debendra Das Sharma ,  Harshit Poladia ,  Kanaka Lakshmi Gadey Naga Venkata

IPC: G06F1/32 ,  G06F13/40

CPC classification number: G06F1/3253 ,  G06F1/3278 ,  G06F13/4027 ,  Y02D10/151 ,  Y02D10/157 ,  Y02D50/20

Abstract: A method of staggering lanes in a peripheral component interconnect express (PCI-Express) port is described herein. The method includes initiating the port to enter or exit an electrical idle state. The method also includes forwarding a token to a predetermined lane of the port. Additionally, the method includes turning the predetermined lane ON or OFF by indication to an analog circuit interface. The method also includes forwarding the token to a neighboring lane when a staggering interval timer elapses.

Abstract translation: 本文描述了外围组件互连快速（PCI-Express）端口中的交错通道的方法。 该方法包括启动端口进入或退出电气空闲状态。 该方法还包括将令牌转发到端口的预定通道。 此外，该方法包括通过指示将预定通道打开或关闭到模拟电路接口。 该方法还包括当令牌间隔计时器经过时将令牌转发到相邻车道。

公开(公告)号：US11726939B2

公开(公告)日：2023-08-15

申请号：US17485337

申请日：2021-09-25

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Prahladachar Jayaprakash Bharadwaj ,  Bruce Tennant ,  Mahesh Wagh

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4027 ,  G06F13/4282 ,  G06F2213/0026

Abstract: Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.

公开(公告)号：US20200210366A1

公开(公告)日：2020-07-02

申请号：US16812156

申请日：2020-03-06

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Prahladachar Jayaprakash Bharadwaj ,  Bruce A. Tennant ,  Mahesh Wagh

IPC: G06F13/40 ,  G06F13/42

Abstract: Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.

公开(公告)号：US10691520B2

公开(公告)日：2020-06-23

申请号：US15942186

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Prahladachar Jayaprakash Bharadwaj ,  Alexander Brown ,  Debendra Das Sharma ,  Junaid Thaliyil

IPC: G06F11/07 ,  G06F11/14

Abstract: A packet is identified at a port of a serial data link, and it is determined that the packet is associated with an error. Entry into an error recovery mode is initiated based on the determination that the packet is associated with the error. Entry into the error recovery mode can cause the serial data link to be forced down. In one aspect, forcing the data link down causes all subsequent inbound packets to be dropped and all pending outbound requests and completions to be aborted during the error recovery mode.

公开(公告)号：US20180225167A1

公开(公告)日：2018-08-09

申请号：US15942186

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Prahladachar Jayaprakash Bharadwaj ,  Alexander Brown ,  Debendra Das Sharma ,  Junaid Thaliyil

IPC: G06F11/07 ,  G06F11/14

Abstract: A packet is identified at a port of a serial data link, and it is determined that the packet is associated with an error. Entry into an error recovery mode is initiated based on the determination that the packet is associated with the error. Entry into the error recovery mode can cause the serial data link to be forced down. In one aspect, forcing the data link down causes all subsequent inbound packets to be dropped and all pending outbound requests and completions to be aborted during the error recovery mode.

公开(公告)号：US20220114128A1

公开(公告)日：2022-04-14

申请号：US17559002

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Michelle Jen ,  Debendra Das Sharma ,  Bruce Tennant ,  Prahladachar Jayaprakash Bharadwaj

IPC: G06F13/40 ,  H04L69/16 ,  G06F1/3237 ,  G06F13/42

Abstract: Methods and apparatuses associated with a secure stream protocol for a serial interconnect are disclosed herein. In embodiments, an apparatus comprises a transmitter and a receiver. The transmitter and receiver are configured to transmit and receive transaction layer data packets through a link, the transaction layer data packets including indicators associated with transmission of order set transmitted after a predetermined number of data blocks, when the transmission is during a header suppression mode. Additional features and other embodiments are also disclosed.

公开(公告)号：US11232058B2

公开(公告)日：2022-01-25

申请号：US16554974

申请日：2019-08-29

Applicant: Intel Corporation

Inventor： Michelle Jen ,  Debendra Das Sharma ,  Bruce Tennant ,  Prahladachar Jayaprakash Bharadwaj

IPC: G06F13/40 ,  G06F1/3237 ,  H04L29/06 ,  G06F13/42 ,  G06F13/38

Abstract: Methods and apparatuses associated with a secure stream protocol for a serial interconnect are disclosed herein. In embodiments, an apparatus comprises a transmitter and a receiver. The transmitter and receiver are configured to transmit and receive transaction layer data packets through a link, the transaction layer data packets including indicators associated with transmission of order set transmitted after a predetermined number of data blocks, when the transmission is during a header suppression mode. Additional features and other embodiments are also disclosed.

公开(公告)号：US20220012203A1

公开(公告)日：2022-01-13

申请号：US17485337

申请日：2021-09-25

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Prahladachar Jayaprakash Bharadwaj ,  Bruce A. Tennant ,  Mahesh Wagh

IPC: G06F13/40 ,  G06F13/42

Abstract: Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.