公开(公告)号：US20220114128A1

公开(公告)日：2022-04-14

申请号：US17559002

申请日：2021-12-22

申请人： Intel Corporation

发明人： Michelle Jen ,  Debendra Das Sharma ,  Bruce Tennant ,  Prahladachar Jayaprakash Bharadwaj

IPC分类号： G06F13/40 ,  H04L69/16 ,  G06F1/3237 ,  G06F13/42

摘要： Methods and apparatuses associated with a secure stream protocol for a serial interconnect are disclosed herein. In embodiments, an apparatus comprises a transmitter and a receiver. The transmitter and receiver are configured to transmit and receive transaction layer data packets through a link, the transaction layer data packets including indicators associated with transmission of order set transmitted after a predetermined number of data blocks, when the transmission is during a header suppression mode. Additional features and other embodiments are also disclosed.

公开(公告)号：US11232058B2

公开(公告)日：2022-01-25

申请号：US16554974

申请日：2019-08-29

申请人： Intel Corporation

发明人： Michelle Jen ,  Debendra Das Sharma ,  Bruce Tennant ,  Prahladachar Jayaprakash Bharadwaj

IPC分类号： G06F13/40 ,  G06F1/3237 ,  H04L29/06 ,  G06F13/42 ,  G06F13/38

摘要： Methods and apparatuses associated with a secure stream protocol for a serial interconnect are disclosed herein. In embodiments, an apparatus comprises a transmitter and a receiver. The transmitter and receiver are configured to transmit and receive transaction layer data packets through a link, the transaction layer data packets including indicators associated with transmission of order set transmitted after a predetermined number of data blocks, when the transmission is during a header suppression mode. Additional features and other embodiments are also disclosed.

公开(公告)号：US11726939B2

公开(公告)日：2023-08-15

申请号：US17485337

申请日：2021-09-25

申请人： Intel Corporation

发明人： Debendra Das Sharma ,  Michelle C. Jen ,  Prahladachar Jayaprakash Bharadwaj ,  Bruce Tennant ,  Mahesh Wagh

IPC分类号： G06F13/40 ,  G06F13/42

CPC分类号： G06F13/4027 ,  G06F13/4282 ,  G06F2213/0026

摘要： Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.

公开(公告)号：US20190303338A1

公开(公告)日：2019-10-03

申请号：US16266992

申请日：2019-02-04

申请人： Intel Corporation

发明人： Michelle Jen ,  Daniel Froelich ,  Debendra Das Sharma ,  Bruce Tennant ,  Quinn Devine ,  Su Wei Lim

IPC分类号： G06F13/42 ,  G06F13/40 ,  G06F13/38

摘要： An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.

公开(公告)号：US10706003B2

公开(公告)日：2020-07-07

申请号：US16266992

申请日：2019-02-04

申请人： Intel Corporation

发明人： Michelle Jen ,  Daniel Froelich ,  Debendra Das Sharma ,  Bruce Tennant ,  Quinn Devine ,  Su Wei Lim

IPC分类号： G06F13/38 ,  G06F13/42 ,  G06F13/40 ,  H04L29/06 ,  H04L29/08

摘要： An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.

公开(公告)号：US10198394B2

公开(公告)日：2019-02-05

申请号：US15283310

申请日：2016-10-01

申请人： Intel Corporation

发明人： Michelle Jen ,  Dan Froelich ,  Debendra Das Sharma ,  Bruce Tennant ,  Quinn Devine ,  Su Wei Lim

IPC分类号： G06F13/00 ,  G06F13/42 ,  G06F13/38 ,  G06F13/40 ,  H04L29/06 ,  H04L29/08

摘要： An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.

公开(公告)号：US11669481B2

公开(公告)日：2023-06-06

申请号：US17559002

申请日：2021-12-22

申请人： Intel Corporation

发明人： Michelle Jen ,  Debendra Das Sharma ,  Bruce Tennant ,  Prahladachar Jayaprakash Bharadwaj

IPC分类号： G06F13/40 ,  H04L69/16 ,  G06F1/3237 ,  G06F13/42 ,  G06F13/38

CPC分类号： G06F13/4068 ,  G06F1/3237 ,  G06F13/4291 ,  H04L69/161 ,  G06F13/385

摘要： Methods and apparatuses associated with a secure stream protocol for a serial interconnect are disclosed herein. In embodiments, an apparatus comprises a transmitter and a receiver. The transmitter and receiver are configured to transmit and receive transaction layer data packets through a link, the transaction layer data packets including indicators associated with transmission of order set transmitted after a predetermined number of data blocks, when the transmission is during a header suppression mode. Additional features and other embodiments are also disclosed.

公开(公告)号：US11163717B2

公开(公告)日：2021-11-02

申请号：US16921498

申请日：2020-07-06

申请人： Intel Corporation

发明人： Michelle Jen ,  Dan Froelich ,  Debendra Das Sharma ,  Bruce Tennant ,  Quinn Devine ,  Su Wei Lim

IPC分类号： G06F13/42 ,  G06F13/38 ,  G06F13/40 ,  H04L29/06 ,  H04L29/08

摘要： An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.

公开(公告)号：US20210056067A1

公开(公告)日：2021-02-25

申请号：US16921498

申请日：2020-07-06

申请人： Intel Corporation

发明人： Michelle Jen ,  Dan Froelich ,  Debendra Das Sharma ,  Bruce Tennant ,  Quinn Devine ,  Su Wei Lim

IPC分类号： G06F13/42 ,  G06F13/38 ,  G06F13/40

摘要： An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.

公开(公告)号：US20170344512A1

公开(公告)日：2017-11-30

申请号：US15283310

申请日：2016-10-01

申请人： Intel Corporation

发明人： Michelle Jen ,  Dan Froelich ,  Debendra Das Sharma ,  Bruce Tennant ,  Quinn Devine ,  Su Wei Lim

IPC分类号： G06F13/42 ,  G06F13/40 ,  H04L29/08

CPC分类号： G06F13/4282 ,  G06F13/385 ,  G06F13/387 ,  G06F13/4068 ,  H04L67/1095 ,  H04L69/08

摘要： An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.