公开(公告)号：US08575589B2

公开(公告)日：2013-11-05

申请号：US12271434

申请日：2008-11-14

Applicant: Hiroyuki Nagashima ,  Koichi Kubo ,  Hirofumi Inoue

Inventor： Hiroyuki Nagashima ,  Koichi Kubo ,  Hirofumi Inoue

IPC: H01L29/06

CPC classification number: H01L27/2463 ,  H01L27/101 ,  H01L27/112 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

Abstract: A nonvolatile semiconductor memory device includes a plurality of first lines; a plurality of second lines crossing the plurality of first lines; a plurality of memory cells each connected at an intersection of the first and second lines between both lines and including a variable resistor operative to store information in accordance with a variation in resistance; and a protection film covering the side of the variable resistor to suppress migration of cations at the side of the variable resistor.

Abstract translation: 非易失性半导体存储器件包括多条第一线; 多条第二线穿过多条第一线; 多个存储单元，每个存储单元分别连接在两条线之间的第一和第二线的交点处，并且包括可变电阻，用于根据电阻的变化存储信息; 以及覆盖可变电阻器一侧的保护膜，以抑制可变电阻器一侧的阳离子迁移。

公开(公告)号：US08469164B2

公开(公告)日：2013-06-25

申请号：US12298196

申请日：2007-04-10

Applicant: Takuhiro Kondo ,  Hirofumi Inoue

Inventor： Takuhiro Kondo ,  Hirofumi Inoue

IPC: F16F9/34

CPC classification number: F16F15/03 ,  B60G13/001 ,  B60G15/062 ,  B60G15/065 ,  B60G17/0157 ,  B60G17/021 ,  B60G2202/312 ,  B60G2202/32 ,  F16F9/0209 ,  F16F9/06 ,  F16F9/18 ,  F16F2232/04 ,  F16F2232/06

Abstract: A damper (D1) comprising an actuator A connected to a sprung member (B) side of a vehicle, the actuator having a motion converting mechanism (T) for converting a linear motion into a rotational motion and a motor (M) to which the rotational motion resulting from the conversion by the motion converting mechanism (T) is transmitted; a hydraulic damper (E), the hydraulic damper (E) having a cylinder (C), a piston (P) inserted slidably into the cylinder (C) and defining two pressure chambers within the cylinder (C), and a rod (R) connected at one end thereof to the piston (P), the linear motion of the actuator (A) being transmitted to one of the rod (R) and the cylinder (C), the other of the rod (R) and the cylinder (C) being connected to an unsprung member (W) side of the vehicle; a spring (1) accommodated within one of the two pressure chambers and biasing the hydraulic damper (E) in a damper compressing direction; and a spring (2) accommodated within the other pressure chamber and biasing the hydraulic damper (E) in a damper extending direction.

Abstract translation: 一种阻尼器（D1），包括连接到车辆的弹簧构件（B）侧的致动器A，所述致动器具有用于将直线运动转换为旋转运动的运动转换机构（T）和马达（M），所述运动转换机构 传送由运动转换机构（T）的转换产生的旋转运动; 液压阻尼器（E），具有气缸（C）的液压阻尼器（E），可滑动地插入气缸（C）中并限定气缸（C）内的两个压力室的活塞（P）和杆（R ），致动器（A）的直线运动传递到杆（R）和气缸（C）中的一个，杆（R）和气缸（C）中的另一个 （C）连接到车辆的簧下部件（W）侧; 容纳在所述两个压力室中的一个内的弹簧（1），并且在阻尼器压缩方向上偏置所述液压阻尼器（E） 以及容纳在另一个压力室内的弹簧（2），并且在阻尼器延伸方向上偏压液压阻尼器（E）。

公开(公告)号：US08467225B2

公开(公告)日：2013-06-18

申请号：US12747290

申请日：2008-09-09

Applicant: Hirofumi Inoue

Inventor： Hirofumi Inoue

IPC: G11C11/00

CPC classification number: G11C7/12 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2213/11 ,  G11C2213/12 ,  G11C2213/72

Abstract: A semiconductor memory device includes a plurality of parallel word lines, a plurality of parallel bit lines formed crossing the plurality of word lines, and a plurality of memory cells arranged at intersections of the word lines and the bit lines. Each memory cell has one end connected to the word line and the other end connected to the bit line. The device also comprises a drive circuit operative to selectively apply a voltage for data read/write across the word line and the bit line. It further comprises a sense amplifier circuit connected to the plurality of bit lines and operative to read/write data stored in the memory cell. The device also comprises a bit-line drive auxiliary circuit operative to selectively adjust the potentials on the plurality of bit lines based on data read out of the memory cell by the sense amplifier circuit.

Abstract translation: 半导体存储器件包括多条并行字线，与多条字线交叉形成的多条并行位线，以及布置在字线和位线的交点处的多个存储单元。 每个存储单元的一端连接到字线，另一端连接到位线。 该装置还包括驱动电路，其操作以选择性地施加跨越字线和位线的数据读/写电压。 它还包括连接到多个位线的读出放大器电路，并用于读/写存储在存储单元中的数据。 该装置还包括位线驱动辅助电路，其可操作以基于由读出放大器电路从存储单元读出的数据选择性地调整多个位线上的电位。

公开(公告)号：US08259489B2

公开(公告)日：2012-09-04

申请号：US12677017

申请日：2008-09-09

Applicant: Hiroyuki Nagashima ,  Hirofumi Inoue ,  Haruki Toda

Inventor： Hiroyuki Nagashima ,  Hirofumi Inoue ,  Haruki Toda

IPC: G11C11/00

CPC classification number: H01L27/101 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0009 ,  G11C13/004 ,  G11C13/0064 ,  G11C2013/0054 ,  G11C2013/0073 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72

Abstract: A nonvolatile semiconductor memory device comprises a memory cell array of electrically erasable programmable nonvolatile memory cells arranged in matrix, each memory cell using a variable resistor. A pulse generator is operative to generate plural types of write pulses for varying the resistance of the variable resistor in three or more stages based on ternary or higher write data. A selection circuit is operative to select a write target memory cell from the memory cell array based on a write address and supply the write pulse generated from the pulse generator to the selected memory cell.

Abstract translation: 非易失性半导体存储器件包括以矩阵形式布置的电可擦除可编程非易失性存储单元的存储单元阵列，每个存储单元使用可变电阻器。 脉冲发生器用于产生多种类型的写入脉冲，用于基于三进制或更高写入数据在三个或更多个阶段中改变可变电阻器的电阻。 选择电路可操作以基于写地址从存储单元阵列中选择写入目标存储单元，并将从脉冲发生器产生的写入脉冲提供给所选存储单元。

公开(公告)号：US08120942B2

公开(公告)日：2012-02-21

申请号：US12559931

申请日：2009-09-15

Applicant: Takeshi Yamaguchi ,  Mariko Hayashi ,  Hirofumi Inoue ,  Takeshi Araki ,  Koichi Kubo

Inventor： Takeshi Yamaguchi ,  Mariko Hayashi ,  Hirofumi Inoue ,  Takeshi Araki ,  Koichi Kubo

IPC: G11C11/00

CPC classification number: G11C13/0007 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/33 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/1021

Abstract: A memory array includes a memory cell, the memory cell being disposed between a first line and a second line and being configured by a variable resistor and a rectifier connected in series. The variable resistor is a mixture of silicon oxide (SiO2) and a transition metal oxide, a proportion of the transition metal oxide being set to 55˜80%.

Abstract translation: 存储器阵列包括存储器单元，存储单元设置在第一线路和第二线路之间，并且由可变电阻器和串联连接的整流器构成。 可变电阻器是氧化硅（SiO 2）和过渡金属氧化物的混合物，过渡金属氧化物的比例设定为55〜80％。

公开(公告)号：US08085585B2

公开(公告)日：2011-12-27

申请号：US13158098

申请日：2011-06-10

Applicant: Hiroyuki Nagashima ,  Hirofumi Inoue

Inventor： Hiroyuki Nagashima ,  Hirofumi Inoue

IPC: G11C11/00

CPC classification number: G11C8/14 ,  G11C5/02 ,  G11C5/063 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0028 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/72 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor memory device includes a memory block having a three-dimensional memory cell array structure in which memory cell arrays are stacked, the memory cell array including: a plurality of first interconnections which are parallel to one another; a plurality of second interconnections which are formed so as to intersect with the plurality of first interconnections, the second interconnections being parallel to one another; and a memory cell which is disposed in each intersection portion of the first interconnection and the second interconnection, one end of the memory cell being connected to the first interconnection, the other end of the memory cell being connected to the second interconnection. The first interconnection disposed between the adjacent memory cell arrays is shared by memory cells above and below the first interconnection, and the vertically-overlapping first interconnections are connected to each other.

Abstract translation: 一种半导体存储器件包括具有堆叠存储单元阵列的三维存储单元阵列结构的存储块，所述存储单元阵列包括：彼此平行的多个第一互连; 多个第二互连形成为与所述多个第一互连相交，所述第二互连彼此平行; 以及存储单元，其设置在所述第一互连和所述第二互连的每个交叉部分中，所述存储单元的一端连接到所述第一互连，所述存储单元的另一端连接到所述第二互连。 设置在相邻存储单元阵列之间的第一互连由第一互连之上和之下的存储单元共享，并且垂直重叠的第一互连彼此连接。

公开(公告)号：US20110298399A1

公开(公告)日：2011-12-08

申请号：US13201962

申请日：2009-07-08

Applicant: Atsushi Ogawa ,  Motohiko Honma ,  Hirofumi Inoue

Inventor： Atsushi Ogawa ,  Motohiko Honma ,  Hirofumi Inoue

IPC: H02K7/06

CPC classification number: H02P3/12 ,  B60G17/06 ,  B60G2300/60 ,  F16F15/03 ,  F16F2232/06

Abstract: A vehicle damper including an electromagnetic damper configured to generate a damping force with respect to a motion of a sprung portion and an unsprung portion toward each other and a motion thereof away from each other and includes: an electromagnetic motor; a motion converting mechanism; and an external circuit which is disposed outside the electromagnetic motor and including a first connection passage and a second connection passage and which includes a battery-device connection circuit for connecting the motor and a battery device and a battery-device-connection-circuit-current adjuster configured to adjust an electric current that flows in the battery-device connection circuit, wherein the damper system further includes an external-circuit controller configured to control an electric current that flows in the electromagnetic motor by controlling the external circuit and configured to control a flow of an electric current between the battery device and the electromagnetic motor by controlling the battery-device-connection-circuit-current adjuster.

Abstract translation: 一种车辆阻尼器，包括电磁阻尼器，其构造成相对于弹簧部分和簧下部分相对于彼此的运动产生阻尼力，并且其运动彼此远离，并且包括：电磁马达; 运动转换机制; 以及外部电路，其设置在所述电磁电动机的外部并且包括第一连接通道和第二连接通道，并且包括用于连接所述电动机和电池装置的电池装置连接电路以及电池装置连接电路电流 调整器，被配置为调节在电池装置连接电路中流动的电流，其中所述阻尼器系统还包括外部电路控制器，其被配置为通过控制所述外部电路来控制在所述电磁电动机中流动的电流，并且被配置为控制 通过控制电池装置连接电路电流调节器，在电池装置和电磁马达之间流动电流。

公开(公告)号：US08031508B2

公开(公告)日：2011-10-04

申请号：US12266879

申请日：2008-11-07

Applicant: Haruki Toda ,  Hirofumi Inoue ,  Hiroto Nakai

Inventor： Haruki Toda ,  Hirofumi Inoue ,  Hiroto Nakai

IPC: G11C11/00

CPC classification number: G11C13/00 ,  G11C5/063 ,  G11C8/14 ,  G11C11/56 ,  G11C13/0028 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/71 ,  G11C2213/72

Abstract: A resistance change memory device includes: a memory cell array with memory cells arranged therein, the memory cell having a variable resistance element for storing a rewritable resistance value; a reference cell formed of the same memory cells as those set in a high resistance state in the memory cell array, the reference cell being trimmed with selection of the number of parallel-connected memory cells to have a reference current value used for detecting data in the memory cell array; and a sense amplifier configured to compare a cell current value of a memory cell selected in the memory cell array with the reference current value of the reference cell.

Abstract translation: 电阻变化存储器件包括：存储单元阵列，其中布置有存储单元，所述存储单元具有用于存储可重写电阻值的可变电阻元件; 由与存储单元阵列中的高电阻状态相同的存储单元形成的参考单元，通过选择并联连接的存储单元的数量来修整参考单元以具有用于检测数据的参考电流值 存储单元阵列; 以及读出放大器，被配置为将存储单元阵列中选择的存储单元的单元电流值与参考单元的参考电流值进行比较。

公开(公告)号：US20110103128A1

公开(公告)日：2011-05-05

申请号：US12882685

申请日：2010-09-15

Applicant: Hiroshi Kanno ,  Reika Ichihara ,  Takayuki Tsukamoto ,  Kenichi Murooka ,  Hirofumi Inoue

Inventor： Hiroshi Kanno ,  Reika Ichihara ,  Takayuki Tsukamoto ,  Kenichi Murooka ,  Hirofumi Inoue

IPC: G11C11/00 ,  G11C7/00

CPC classification number: G11C7/02 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0064 ,  G11C13/0097 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/72

Abstract: Nonvolatile semiconductor memory device of an embodiment includes: a memory cell array including a plurality of first and second lines intersecting each other and plural memory cells provided at intersections of the first and second lines and having data written and erased upon application of voltages of the same polarity; and a writing circuit configured to select first and second lines and supply a set or reset pulse to the memory cell through the selected first and second lines. In an erase operation, the writing circuit repeatedly supplies the reset pulse to a selected memory cell until data is erased, by increasing or decreasing voltage level and voltage application time of the reset pulse within a reset region. The reset region, or an aggregate of combinations of voltage level and voltage application time of the reset pulse, is a region where voltage level and voltage application time are negatively correlated.

Abstract translation: 一个实施例的非易失性半导体存储器件包括：存储单元阵列，包括彼此相交的多个第一和第二线，以及设置在第一和第二线的交点处的多个存储单元，并且在施加相同的电压时写入和擦除数据 极性; 以及写入电路，被配置为选择第一和第二行，并且通过所选择的第一和第二行向存储器单元提供置位或复位脉冲。 在擦除操作中，写入电路通过增加或减小复位区域内的复位脉冲的电压电平和电压施加时间，将复位脉冲重复地提供给所选择的存储单元，直到数据被擦除。 复位区域或复位脉冲的电压电平和电压施加时间的组合的总和是电压电平和电压施加时间呈负相关的区域。

公开(公告)号：US20100025946A1

公开(公告)日：2010-02-04

申请号：US12440183

申请日：2007-08-28

Applicant: Hirofumi Inoue ,  Hideshi Watanabe ,  Takuhiro Kondo

Inventor： Hirofumi Inoue ,  Hideshi Watanabe ,  Takuhiro Kondo

IPC: B60G17/00

CPC classification number: B60G17/0157 ,  B60G15/08 ,  B60G17/0155 ,  B60G17/018 ,  B60G17/0521 ,  B60G17/06 ,  B60G2202/152 ,  B60G2202/314 ,  B60G2202/42 ,  B60G2204/126 ,  B60G2204/419 ,  B60G2204/4232 ,  B60G2204/62 ,  B60G2400/0511 ,  B60G2400/0516 ,  B60G2400/102 ,  B60G2400/104 ,  B60G2400/106 ,  B60G2400/204 ,  B60G2400/252 ,  B60G2400/33 ,  B60G2400/382 ,  B60G2400/39 ,  B60G2400/41 ,  B60G2400/716 ,  B60G2400/73 ,  B60G2500/201 ,  B60G2500/2021 ,  B60G2500/203 ,  B60G2500/30 ,  B60G2600/02 ,  B60G2600/07 ,  B60G2600/08 ,  B60G2600/182 ,  B60G2800/012 ,  B60G2800/014 ,  B60G2800/162 ,  B60G2800/80 ,  B60G2800/9122 ,  B60G2800/914 ,  B60G2800/916 ,  F16F2232/04 ,  F16F2232/06

Abstract: It is an object of the invention to provide a suspension system configured to execute a control for avoiding a state in which an operation of an electric motor which is a power source of an electromagnetic actuator is kept halted at a certain operational position while the motor is generating a motor force. Where a target rotational position of the motor becomes equal to a specific operational position (e.g., a rotational position at which an electrifying current amount of one phase reaches a peak value), a control for shifting the target rotational position by δθ is executed. Where the rotational position of the motor is kept located at the certain position for a time period longer than a prescribed time, a control for changing the rotational position of the motor is executed. According to the present suspension system, it is possible to suppress imbalance in heat generation in the motor and to thereby reduce a load to be applied to the motor. Accordingly, a suspension system with high utility is realized.

Abstract translation: 本发明的目的是提供一种悬架系统，该悬架系统被配置为执行控制，以避免将电动机作为电动机的电源的电动机的动作在马达为 产生马达力。 在电动机的目标旋转位置变得等于特定操作位置（例如，一相的通电电流量达到峰值的旋转位置）的情况下，执行用目标旋转位置移动deltatheta的控制。 在电动机的旋转位置保持在特定位置上比规定时间长的时间的情况下，执行用于改变电动机的旋转位置的控制。 根据本悬架系统，可以抑制电动机的发热不平衡，从而减小对电动机施加的负荷。 因此，实现了高效率的悬架系统。