公开(公告)号：US08575589B2

公开(公告)日：2013-11-05

申请号：US12271434

申请日：2008-11-14

Applicant: Hiroyuki Nagashima ,  Koichi Kubo ,  Hirofumi Inoue

Inventor： Hiroyuki Nagashima ,  Koichi Kubo ,  Hirofumi Inoue

IPC: H01L29/06

CPC classification number: H01L27/2463 ,  H01L27/101 ,  H01L27/112 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

Abstract: A nonvolatile semiconductor memory device includes a plurality of first lines; a plurality of second lines crossing the plurality of first lines; a plurality of memory cells each connected at an intersection of the first and second lines between both lines and including a variable resistor operative to store information in accordance with a variation in resistance; and a protection film covering the side of the variable resistor to suppress migration of cations at the side of the variable resistor.

Abstract translation: 非易失性半导体存储器件包括多条第一线; 多条第二线穿过多条第一线; 多个存储单元，每个存储单元分别连接在两条线之间的第一和第二线的交点处，并且包括可变电阻，用于根据电阻的变化存储信息; 以及覆盖可变电阻器一侧的保护膜，以抑制可变电阻器一侧的阳离子迁移。

公开(公告)号：US20090121208A1

公开(公告)日：2009-05-14

申请号：US12271434

申请日：2008-11-14

Applicant: Hiroyuki Nagashima ,  Koichi Kubo ,  Hirofumi Inoue

Inventor： Hiroyuki Nagashima ,  Koichi Kubo ,  Hirofumi Inoue

IPC: H01L47/00 ,  H01L21/00 ,  H01L21/4763

CPC classification number: H01L27/2463 ,  H01L27/101 ,  H01L27/112 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

Abstract: A nonvolatile semiconductor memory device comprises a plurality of first lines; a plurality of second lines crossing the plurality of first lines; a plurality of memory cells each connected at an intersection of the first and second lines between both lines and including a variable resistor operative to store information in accordance with a variation in resistance; and a protection film covering the side of the variable resistor to suppress migration of cations at the side of the variable resistor.

Abstract translation: 非易失性半导体存储器件包括多条第一线; 多条第二线穿过多条第一线; 多个存储单元，每个存储单元分别连接在两条线之间的第一和第二线的交点处，并且包括可变电阻，用于根据电阻的变化存储信息; 以及覆盖可变电阻器一侧的保护膜，以抑制可变电阻器一侧的阳离子迁移。

公开(公告)号：US08300444B2

公开(公告)日：2012-10-30

申请号：US12680582

申请日：2008-10-17

Applicant: Hiroyuki Nagashima ,  Koichi Kubo ,  Yasuyuki Fukuda

Inventor： Hiroyuki Nagashima ,  Koichi Kubo ,  Yasuyuki Fukuda

IPC: G11C11/00

CPC classification number: G11C13/0007 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/3413 ,  G11C16/3463 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/34 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72

Abstract: A nonvolatile semiconductor memory device comprises a memory cell array of electrically erasable programmable nonvolatile memory cells arranged in matrix, each memory cell using a variable resistor. A pulse generator generates plural types of write pulses for varying the resistance of the variable resistor based on write data. A selection circuit applies write pulses generated by the pulse generator to the memory cell. A sense amplifier executes verify read to the memory cell. A status decision circuit decides the verify result based on the output from the sense amplifier. A control circuit executes additional write to the memory cell based on the verify result from the status decision circuit.

Abstract translation: 非易失性半导体存储器件包括以矩阵形式布置的电可擦除可编程非易失性存储单元的存储单元阵列，每个存储单元使用可变电阻器。 脉冲发生器产生用于根据写入数据改变可变电阻器的电阻的多种类型的写入脉冲。 选择电路将由脉冲发生器产生的写脉冲施加到存储单元。 读出放大器对存储单元执行验证读取。 状态判定电路根据读出放大器的输出决定验证结果。 控制电路基于来自状态判定电路的验证结果对存储器单元执行附加写入。

公开(公告)号：US20100226164A1

公开(公告)日：2010-09-09

申请号：US12680582

申请日：2008-10-17

Applicant: Hiroyuki Nagashima ,  Koichi Kubo ,  Yasuyuki Fukuda

Inventor： Hiroyuki Nagashima ,  Koichi Kubo ,  Yasuyuki Fukuda

IPC: G11C11/00 ,  G11C7/00

CPC classification number: G11C13/0007 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/3413 ,  G11C16/3463 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/34 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72

Abstract: A nonvolatile semiconductor memory device comprises a memory cell array of electrically erasable programmable nonvolatile memory cells arranged in matrix, each memory cell using a variable resistor. A pulse generator generates plural types of write pulses for varying the resistance of the variable resistor based on write data. A selection circuit applies write pulses generated by the pulse generator to the memory cell. A sense amplifier executes verify read to the memory cell. A status decision circuit decides the verify result based on the output from the sense amplifier. A control circuit executes additional write to the memory cell based on the verify result from the status decision circuit.

Abstract translation: 非易失性半导体存储器件包括以矩阵形式布置的电可擦除可编程非易失性存储单元的存储单元阵列，每个存储单元使用可变电阻器。 脉冲发生器产生用于根据写入数据改变可变电阻器的电阻的多种类型的写入脉冲。 选择电路将由脉冲发生器产生的写脉冲施加到存储单元。 读出放大器对存储单元执行验证读取。 状态判定电路根据读出放大器的输出决定验证结果。 控制电路基于来自状态判定电路的验证结果对存储器单元执行附加写入。

公开(公告)号：US20110242875A1

公开(公告)日：2011-10-06

申请号：US13058952

申请日：2009-06-24

Applicant: Hiroyuki Nagashima ,  Hirofumi Inoue

Inventor： Hiroyuki Nagashima ,  Hirofumi Inoue

IPC: G11C11/00

CPC classification number: G11C13/003 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/31 ,  G11C2213/72

Abstract: A nonvolatile semiconductor memory device comprises a cell array including a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells arranged in matrix and connected at intersections of the first and second lines between both lines, each memory cell containing a serial circuit of an electrically erasable programmable variable resistive element of which resistance is nonvolatilely stored as data and a non-ohmic element; and a plurality of access circuits operative to simultaneously access the memory cells physically separated from each other in the cell array.

Abstract translation: 一种非易失性半导体存储器件，包括一个单元阵列，该单元阵列包括多个第一线，与该多条第一线相交的多个第二线，以及多个存储单元，被布置成矩阵并连接在两条线之间的第一和第二线的交点处 每个存储单元包含其中电阻被非易失性地存储为数据的电可擦除可编程可变电阻元件和非欧姆元件的串行电路; 以及多个访问电路，其操作以同时访问在单元阵列中彼此物理分离的存储单元。

公开(公告)号：US20100328988A1

公开(公告)日：2010-12-30

申请号：US12677017

申请日：2008-09-09

Applicant: Hiroyuki Nagashima ,  Hirofumi Inoue ,  Haruki Toda

Inventor： Hiroyuki Nagashima ,  Hirofumi Inoue ,  Haruki Toda

IPC: G11C11/00

CPC classification number: H01L27/101 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0009 ,  G11C13/004 ,  G11C13/0064 ,  G11C2013/0054 ,  G11C2013/0073 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72

Abstract: A nonvolatile semiconductor memory device comprises a memory cell array of electrically erasable programmable nonvolatile memory cells arranged in matrix, each memory cell using a variable resistor. A pulse generator is operative to generate plural types of write pulses for varying the resistance of the variable resistor in three or more stages based on ternary or higher write data. A selection circuit is operative to select a write target memory cell from the memory cell array based on a write address and supply the write pulse generated from the pulse generator to the selected memory cell.

Abstract translation: 非易失性半导体存储器件包括以矩阵形式布置的电可擦除可编程非易失性存储单元的存储单元阵列，每个存储单元使用可变电阻器。 脉冲发生器用于产生多种类型的写入脉冲，用于基于三进制或更高写入数据在三个或更多个阶段中改变可变电阻器的电阻。 选择电路可操作以基于写地址从存储单元阵列中选择写入目标存储单元，并将从脉冲发生器产生的写入脉冲提供给所选存储单元。

公开(公告)号：US08259489B2

公开(公告)日：2012-09-04

申请号：US12677017

申请日：2008-09-09

Applicant: Hiroyuki Nagashima ,  Hirofumi Inoue ,  Haruki Toda

Inventor： Hiroyuki Nagashima ,  Hirofumi Inoue ,  Haruki Toda

IPC: G11C11/00

CPC classification number: H01L27/101 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0009 ,  G11C13/004 ,  G11C13/0064 ,  G11C2013/0054 ,  G11C2013/0073 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72

Abstract: A nonvolatile semiconductor memory device comprises a memory cell array of electrically erasable programmable nonvolatile memory cells arranged in matrix, each memory cell using a variable resistor. A pulse generator is operative to generate plural types of write pulses for varying the resistance of the variable resistor in three or more stages based on ternary or higher write data. A selection circuit is operative to select a write target memory cell from the memory cell array based on a write address and supply the write pulse generated from the pulse generator to the selected memory cell.

Abstract translation: 非易失性半导体存储器件包括以矩阵形式布置的电可擦除可编程非易失性存储单元的存储单元阵列，每个存储单元使用可变电阻器。 脉冲发生器用于产生多种类型的写入脉冲，用于基于三进制或更高写入数据在三个或更多个阶段中改变可变电阻器的电阻。 选择电路可操作以基于写地址从存储单元阵列中选择写入目标存储单元，并将从脉冲发生器产生的写入脉冲提供给所选存储单元。

公开(公告)号：US08085585B2

公开(公告)日：2011-12-27

申请号：US13158098

申请日：2011-06-10

Applicant: Hiroyuki Nagashima ,  Hirofumi Inoue

Inventor： Hiroyuki Nagashima ,  Hirofumi Inoue

IPC: G11C11/00

CPC classification number: G11C8/14 ,  G11C5/02 ,  G11C5/063 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0028 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/72 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor memory device includes a memory block having a three-dimensional memory cell array structure in which memory cell arrays are stacked, the memory cell array including: a plurality of first interconnections which are parallel to one another; a plurality of second interconnections which are formed so as to intersect with the plurality of first interconnections, the second interconnections being parallel to one another; and a memory cell which is disposed in each intersection portion of the first interconnection and the second interconnection, one end of the memory cell being connected to the first interconnection, the other end of the memory cell being connected to the second interconnection. The first interconnection disposed between the adjacent memory cell arrays is shared by memory cells above and below the first interconnection, and the vertically-overlapping first interconnections are connected to each other.

Abstract translation: 一种半导体存储器件包括具有堆叠存储单元阵列的三维存储单元阵列结构的存储块，所述存储单元阵列包括：彼此平行的多个第一互连; 多个第二互连形成为与所述多个第一互连相交，所述第二互连彼此平行; 以及存储单元，其设置在所述第一互连和所述第二互连的每个交叉部分中，所述存储单元的一端连接到所述第一互连，所述存储单元的另一端连接到所述第二互连。 设置在相邻存储单元阵列之间的第一互连由第一互连之上和之下的存储单元共享，并且垂直重叠的第一互连彼此连接。

公开(公告)号：US20090137112A1

公开(公告)日：2009-05-28

申请号：US12275741

申请日：2008-11-21

Applicant: Hideyuki TABATA ,  Hirofumi Inoue ,  Hiroyuki Nagashima ,  Kohichi Kubo

Inventor： Hideyuki TABATA ,  Hirofumi Inoue ,  Hiroyuki Nagashima ,  Kohichi Kubo

IPC: H01L21/768

CPC classification number: H01L27/2418 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1675

Abstract: A method of manufacturing nonvolatile semiconductor memory devices comprises forming a first wiring material; and stacking memory cell materials on the first wiring material, which configure memory cells each including a variable resistor operative to nonvolatilely store information in accordance with variation in resistance. The method also comprises forming a plurality of first parallel trenches in the first wiring material and the stacked memory cell materials, the first trenches extending in a first direction, thereby forming first lines extending in the first direction and memory cell materials self-aligned with the first lines and separated by the first trenches. The method further comprises burying an interlayer insulator in the first trenches to form a block body and stacking a second wiring material on the block body. The method also comprises forming a plurality of second parallel trenches in the block body with the second wiring material stacked thereon, the second trenches extending in a second direction crossing the first direction and having a depth reaching the upper surface of the first wiring material, thereby forming second lines extending in the second direction and memory cells self-aligned with the second lines and separated by the first and second trenches.

Abstract translation: 制造非易失性半导体存储器件的方法包括：形成第一布线材料; 以及在第一布线材料上堆叠存储单元材料，其构造每个包括可变电阻器的存储单元，其可操作以根据电阻的变化来非易失性地存储信息。 该方法还包括在第一布线材料和堆叠的存储单元材料中形成多个第一平行沟槽，第一沟槽沿第一方向延伸，从而形成沿第一方向延伸的第一线和与第一方向自对准的存储单元材料 第一条线和第一条沟分开。 该方法还包括在第一沟槽中埋设层间绝缘体以形成块体并将第二布线材料堆叠在块体上。 该方法还包括在堆叠在其上的第二布线材料的块体中形成多个第二平行沟槽，第二沟槽沿与第一方向交叉的第二方向延伸并且具有到达第一布线材料的上表面的深度，从而 形成沿着第二方向延伸的第二线和与第二线自对准并由第一和第二沟槽隔开的存储器单元。

公开(公告)号：US08391082B2

公开(公告)日：2013-03-05

申请号：US13099540

申请日：2011-05-03

Applicant: Hiroyuki Nagashima ,  Hirofumi Inoue

Inventor： Hiroyuki Nagashima ,  Hirofumi Inoue

IPC: G11C7/10

CPC classification number: G11C13/0069 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1075 ,  G11C7/22 ,  G11C8/16 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0061 ,  G11C13/0097 ,  G11C2013/0076 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/31 ,  G11C2213/72 ,  G11C2216/24

Abstract: A nonvolatile semiconductor memory device comprises a cell array including plural MATs (unit cell arrays) arranged in matrix, each MAT containing a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells connected at intersections of the first and second lines between both lines, each memory cell containing an electrically erasable programmable variable resistive element of which resistance is stored in a non-volatile manner as data; and a plurality of write/erase circuits connected to the MATs and operative to execute data write or erase to the memory cells inside the MATs in accordance with input data. A part of the plurality of write/erase circuits writes data to memory cells inside a corresponding MAT while another part of the plurality of write/erase circuits erases data from memory cells inside a corresponding MAT at the same time.

Abstract translation: 一种非易失性半导体存储器件，包括一个单元阵列，该单元阵列包括矩阵排列的多个MAT（单元阵列），每个MAT包含多条第一线，与该多条第一线交叉的多条第二线，以及多条存储单元 两行之间的第一和第二行的交点，每个存储单元包含以电阻作为数据以非易失性方式存储的电可擦除可编程可变电阻元件; 以及多个写入/擦除电路，连接到MAT，并根据输入数据对MAT内的存储单元执行数据写入或擦除。 多个写/擦除电路的一部分将数据写入相应MAT内的存储单元，而多个写/擦除电路的另一部分同时从相应MAT内的存储单元擦除数据。