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    Weak Erase After Programming To Improve Data Retention In Charge-Trapping Memory
    2.
    发明申请
    Weak Erase After Programming To Improve Data Retention In Charge-Trapping Memory 有权
    编程后弱化擦除电荷捕获存储器中的数据保留

    公开(公告)号：US20160111164A1

    公开(公告)日：2016-04-21

    申请号：US14518340

    申请日：2014-10-20

    Applicant: SANDISK TECHNOLOGIES INC.

    Inventor： Hong-Yan Chen ,  Yingda Dong ,  Ching-Huang Lu

    IPC: G11C16/14 ,  G11C16/04

    CPC classification number: G11C16/14 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3413

    Abstract: Techniques are provided to improve long term data retention in a charge-trapping memory device. In addition to a primary charge-trapping layer in which most charges are stored, the memory device may include a tunneling layer comprising an engineered tunneling barrier such as oxide-nitride-oxide. The nitride in the tunneling layer may also store some charges after programming. After the programming, a data retention operation is performed which de-traps some electrons from the tunneling layer, in addition to injecting holes into the tunneling layer which form neutral electron-hole dipoles in place of electrons. These mechanisms tend to lower threshold voltage. Additionally, the data retention operation redistributes the electrons and the holes inside the charge-trapping layer, resulting in an increase in threshold voltage which roughly cancels out the decrease when the data retention operation is optimized.

    Abstract translation: 提供技术来改善电荷俘获存储器件中的长期数据保持。 除了存储大多数电荷的主电荷捕获层之外，存储器件可以包括隧道层，其包括工程化隧道势垒，例如氧化物 - 氮化物 - 氧化物。 在编程之后，隧道层中的氮化物也可能存储一些电荷。 在编程之后，除了将空穴注入到形成中性电子 - 空穴偶极子的隧道层中以代替电子之外，还执行了从隧道层去除一些电子的数据保留操作。 这些机制倾向于降低阈值电压。 此外，数据保持操作将电荷和空穴重新分布在电荷俘获层内部，导致阈值电压的增加，这在数据保持操作优化时大致抵消了减少。

    Reduced current program verify in non-volatile memory
    3.
    发明授权
    Reduced current program verify in non-volatile memory 有权
    在非易失性存储器中减少当前程序验证

    公开(公告)号：US09236139B1

    公开(公告)日：2016-01-12

    申请号：US14619875

    申请日：2015-02-11

    Applicant: SanDisk Technologies Inc.

    Inventor： Chun-Hung Lai ,  Shih-Chung Lee

    IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10

    CPC classification number: G11C16/3459 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/3413 ,  G11C16/3427 ,  G11C2211/5621

    Abstract: Reducing peak current and/or power consumption during verify of a non-volatile memory is disclosed. During a program verify, only memory cells in a first physical segment of the selected word line are verified during an initial program loop; memory cells in a different physical segment of the word line are locked out and not verified. The locked out memory cells may be slower to program. During a later program loop, memory cells in all physical segments are program verified. Locked out strings do not conduct a significant current during verify, thus reducing current/power consumption.

    Abstract translation: 公开了在验证非易失性存储器期间降低峰值电流和/或功率消耗。 在程序验证期间，在初始程序循环期间仅验证所选字线的第一物理段中的存储单元; 字线的不同物理段中的存储单元被锁定并未被验证。 锁定的存储单元可能较慢编程。 在稍后的程序循环中，所有物理段中的存储单元都被程序验证。 锁定字符串在验证期间不会导致显着的电流，从而降低电流/功耗。

    Methods of operating nonvolatile memory devices that support efficient error detection
    4.
    发明授权
    Methods of operating nonvolatile memory devices that support efficient error detection 有权
    操作支持高效错误检测的非易失性存储器件的方法

    公开(公告)号：US09053822B2

    公开(公告)日：2015-06-09

    申请号：US13777512

    申请日：2013-02-26

    Applicant: Ji-Sang Lee ,  Moosung Kim ,  Kihwan Choi

    Inventor： Ji-Sang Lee ,  Moosung Kim ,  Kihwan Choi

    IPC: G11C29/00 ,  G11C29/04 ,  G11C16/02 ,  G11C16/04 ,  G11C16/34 ,  G06F11/10 ,  G11C11/56

    CPC classification number: G11C11/5635 ,  G06F11/1048 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/02 ,  G11C16/0483 ,  G11C16/3413 ,  G11C16/3436 ,  G11C16/3454 ,  G11C29/04 ,  G11C2029/0411 ,  G11C2211/5621

    Abstract: Methods of operating nonvolatile memory devices may include identifying one or more multi-bit nonvolatile memory cells in a nonvolatile memory device that have undergone unintentional programming from an erased state to an at least partially programmed state. Errors generated during an operation to program a first plurality of multi-bit nonvolatile memory cells may be detected by performing a plurality of reading operations to generate error detection data and then decoding the error detection data to identify specific cells having errors. A programmed first plurality of multi-bit nonvolatile memory cells and a force-bit data vector, which was modified during the program operation, may be read to support error detection. This data, along with data read from a page buffer associated with the first plurality of multi-bit nonvolatile memory cells, may then be decoded to identify which of the first plurality of multi-bit nonvolatile memory cells are unintentionally programmed cells.

    Abstract translation: 操作非易失性存储器件的方法可以包括识别非易失性存储器件中的一个或多个多位非易失性存储器单元，其经历从擦除状态到至少部分编程状态的无意编程。 可以通过执行多个读取操作来生成错误检测数据，然后解码错误检测数据以识别具有错误的特定单元，来检测在编程第一多个多位非易失性存储器单元的操作期间产生的错误。 可以读取编程的第一多个多位非易失性存储单元和在编程操作期间被修改的强位数据向量，以支持错误检测。 然后可以将该数据连同从与第一多个多位非易失性存储器单元相关联的页面缓冲器读取的数据解码以识别第一多个多位非易失性存储器单元中的哪一个是无意编程的单元。

    Apparatus and method for detecting over-programming condition in multistate memory device
    8.
    发明授权
    Apparatus and method for detecting over-programming condition in multistate memory device 失效
    多状态存储器件中过度编程条件的检测装置及方法

    公开(公告)号：US07457997B2

    公开(公告)日：2008-11-25

    申请号：US10629279

    申请日：2003-07-29

    Applicant: Robert D. Norman ,  Christophe J. Chevallier

    Inventor： Robert D. Norman ,  Christophe J. Chevallier

    IPC: G11C29/00 ,  G11C16/06 ,  G11C16/04 ,  G11C7/00

    CPC classification number: G11C29/765 ,  G06F11/1072 ,  G11C7/1039 ,  G11C11/5621 ,  G11C11/5628 ,  G11C16/04 ,  G11C16/3413 ,  G11C16/3418 ,  G11C16/3463 ,  G11C29/00 ,  G11C29/52 ,  G11C29/76 ,  G11C29/82 ,  G11C2029/0409 ,  G11C2211/5643

    Abstract: An apparatus and method for detecting an over-programming condition in a multistate memory cell. The invention is also directed to identifying the over-programmed cells and providing an alternate location at which to write the data intended for the over-programmed cell. An over-programmed state detection circuit generates an error signal when the data contained in a multistate memory cell is found to be over-programmed relative to its intended programming (threshold voltage level) state. Upon detection of an over-programmed cell, the programming operation of the memory system is modified to discontinue further programming attempts on the cell. The over-programmed state detection circuit is also used to assist in correcting for the over-programming state, permitting the programming error to be compensated for by the memory system.

    Abstract translation: 一种用于检测多态存储器单元中的过编程状态的装置和方法。 本发明还涉及识别过程编程的单元并提供写入用于过程编程单元的数据的备用位置。 当发现包含在多状态存储器单元中的数据相对于其预期编程（阈值电压电平）状态被发现过度编程时，过程编程状态检测电路产生错误信号。 在检测到过度编程的单元时，修改存储器系统的编程操作以中止对单元的进一步编程尝试。 过度编程状态检测电路还用于帮助校正过度编程状态，允许由存储器系统补偿编程错误。

    Nonvolatile semiconductor memory device
    9.
    发明授权
    Nonvolatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US07450417B2

    公开(公告)日：2008-11-11

    申请号：US11637026

    申请日：2006-12-12

    Applicant: Seiji Kaneko ,  Naoki Ueda

    Inventor： Seiji Kaneko ,  Naoki Ueda

    IPC: G11C11/34 ,  G11C16/04

    CPC classification number: G11C16/3454 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3413 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3459 ,  G11C2211/5621

    Abstract: There is provided a nonvolatile semiconductor memory device capable of accelerating writing time and avoiding readout errors of information by eliminating variation in threshold voltage of unselected memory cells. In a nonvolatile semiconductor memory device having a memory cell array with memory cells capable of erasing and programming information, the memory cells store one data value selected from the same number of data values as programming distribution ranges, associated with that the electrical attribute belongs to any one of the more than one programming distribution ranges. The device comprises an erasure means for erasing the selected memory cell to be erased so that its electrical attribute belongs to a erasure distribution range not overlapping any of the programming distribution ranges and a programming means for programming an erased memory cell to be programmed so that its electrical attribute belongs to any one of the programming distribution ranges.

    Abstract translation: 提供一种非易失性半导体存储器件，其能够通过消除未选择的存储单元的阈值电压的变化来加速写入时间并避免信息的读出错误。 在具有具有能够擦除和编程信息的存储器单元的存储单元阵列的非易失性半导体存储器件中，存储器单元存储从与电属性属于任何相关联的编程分配范围相同数量的数据值中选择的一个数据值 多个编程分布范围之一。 该装置包括擦除装置，用于擦除被擦除的所选择的存储单元，使得其电属性属于不与任何编程分布范围重叠的擦除分布范围，以及编程装置，用于对要编程的擦除存储器单元进行编程， 电属性属于编程分布范围中的任何一个。

    METHOD OF PERFORMING AN ERASE OPERATION IN A NON-VOLATILE MEMORY DEVICE
    10.
    发明申请
    METHOD OF PERFORMING AN ERASE OPERATION IN A NON-VOLATILE MEMORY DEVICE 有权
    在非易失性存储器件中执行擦除操作的方法

    公开(公告)号：US20080175069A1

    公开(公告)日：2008-07-24

    申请号：US11951936

    申请日：2007-12-06

    Applicant: Jong Hyun Wang ,  Se Chun Park ,  Seong Hun Park

    Inventor： Jong Hyun Wang ,  Se Chun Park ,  Seong Hun Park

    IPC: G11C16/16

    CPC classification number: G11C16/0483 ,  G11C11/5635 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3413

    Abstract: An erase method having a memory cell array which includes at least one blocks having MLC is disclosed. The erase method includes shifting every threshold voltage distribution into a threshold voltage distribution having highest level by pre-programming every cell in a block selected for erase, performing an erase operation on the pre-programmed memory block, performing a soft program and a verifying operation on the memory block, dividing the memory block into a first group and a second group in case that the memory block is passed, performing a verifying operation on the first group, and performing a soft program and a verifying operation on the first group in case that the first group is not passed, and performing a verifying operation on the second group in case that the first group is passed, and performing a soft program and a verifying operation on the second group in case that the second group is not passed.

    Abstract translation: 公开了一种具有包括具有MLC的至少一个块的存储单元阵列的擦除方法。 擦除方法包括通过预先编程被选择擦除的块中的每个小区，对预先编程的存储块执行擦除操作，执行软程序和验证操作，将每个阈值电压分布转换为具有最高电平的阈值电压分布 在所述存储器块上，在所述存储器块通过的情况下，将所述存储块划分为第一组和第二组，对所述第一组执行验证操作，并且在第一组中执行软程序和验证操作 第一组未通过，并且在第一组通过的情况下对第二组执行验证操作，并且在不通过第二组的情况下对第二组执行软程序和验证操作。

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