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    Reduced current program verify in non-volatile memory
    1.
    发明授权
    Reduced current program verify in non-volatile memory 有权
    在非易失性存储器中减少当前程序验证

    公开(公告)号：US09236139B1

    公开(公告)日：2016-01-12

    申请号：US14619875

    申请日：2015-02-11

    Applicant: SanDisk Technologies Inc.

    Inventor： Chun-Hung Lai ,  Shih-Chung Lee

    IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10

    CPC classification number: G11C16/3459 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/3413 ,  G11C16/3427 ,  G11C2211/5621

    Abstract: Reducing peak current and/or power consumption during verify of a non-volatile memory is disclosed. During a program verify, only memory cells in a first physical segment of the selected word line are verified during an initial program loop; memory cells in a different physical segment of the word line are locked out and not verified. The locked out memory cells may be slower to program. During a later program loop, memory cells in all physical segments are program verified. Locked out strings do not conduct a significant current during verify, thus reducing current/power consumption.

    Abstract translation: 公开了在验证非易失性存储器期间降低峰值电流和/或功率消耗。 在程序验证期间，在初始程序循环期间仅验证所选字线的第一物理段中的存储单元; 字线的不同物理段中的存储单元被锁定并未被验证。 锁定的存储单元可能较慢编程。 在稍后的程序循环中，所有物理段中的存储单元都被程序验证。 锁定字符串在验证期间不会导致显着的电流，从而降低电流/功耗。

    Select gate bias during program of non-volatile storage
    3.
    发明授权
    Select gate bias during program of non-volatile storage 有权
    在非易失性存储程序期间选择栅极偏置

    公开(公告)号：US09087601B2

    公开(公告)日：2015-07-21

    申请号：US13736802

    申请日：2013-01-08

    Applicant: SanDisk Technologies Inc.

    Inventor： Deepanshu Dutta ,  Shinji Sato ,  Fumiko Yano ,  Chun-Hung Lai ,  Masaaki Higashitani

    IPC: G11C11/34 ,  G11C16/34 ,  G11C16/10 ,  G11C11/56 ,  G11C16/24 ,  G11C16/04 ,  G11C16/12

    CPC classification number: G11C16/3427 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24

    Abstract: Techniques disclosed herein may prevent program disturb by preventing a select transistor of an unselected NAND string from unintentionally turning on. The Vgs of a select transistor of a NAND string may be lowered from one programming pulse to the next programming pulse multiple times. The select transistor may be a drain side select transistor or a source side select transistor. Progressively lowering the Vgs of the select transistor of an unselected NAND string as programming progresses may prevent the select transistor from unintentionally turning on. Therefore, program disturb is prevented or reduced. Vgs may be lowered by applying a lower voltage to a select line associated with the select transistor. Vgs may be lowered by applying a higher voltage to bit lines associated with the unselected NAND strings as programming progresses. Vgs may be lowered by applying a higher voltage to a common source line as programming progresses.

    Abstract translation: 本文公开的技术可以通过防止未选择的NAND串的选择晶体管无意地导通来阻止程序干扰。 NAND串的选择晶体管的Vgs可以从一个编程脉冲多次降低到下一个编程脉冲。 选择晶体管可以是漏极侧选择晶体管或源极侧选择晶体管。 随着编程进行，逐渐降低未选择的NAND串的选择晶体管的Vgs可以防止选择晶体管无意地导通。 因此，防止或减少程序干扰。 可以通过对与选择晶体管相关联的选择线施加较低的电压来降低Vgs。 当编程进行时，可以通过对与未选择的NAND串相关联的位线施加更高的电压来降低Vgs。 当编程进行时，Vgs可以通过对公共源极线施加更高的电压来降低。

    DYNAMIC ERASE DEPTH FOR IMPROVED ENDURANCE OF NON-VOLATILE MEMORY
    5.
    发明申请
    DYNAMIC ERASE DEPTH FOR IMPROVED ENDURANCE OF NON-VOLATILE MEMORY 有权
    动态消除深度改善非易失性存储器的耐用性

    公开(公告)号：US20140247666A1

    公开(公告)日：2014-09-04

    申请号：US14195265

    申请日：2014-03-03

    Applicant: SanDisk Technologies, Inc.

    Inventor： Deepanshu Dutta ,  Chun-Hung Lai ,  Shih-Chung Lee ,  Ken Oowada ,  Masaaki Higashitani

    IPC: G11C16/14 ,  G11C16/26 ,  G11C16/34

    CPC classification number: G11C16/14 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/16 ,  G11C16/3427 ,  G11C16/3445 ,  G11C16/349

    Abstract: Improving endurance for non-volatile memory by dynamic erase depth is disclosed. A group of memory cells are erased. Then, at least some of the erased memory cells are programmed. Programming the memory cells typically impacts the erase threshold distribution of those memory cells that were intended to stay erased. The erase depth of the next erase can be adjusted based on how the program operation affects the erase threshold distribution. As one example, the upper tail of the erase distribution is measured after programming. The higher the upper tail, the shallower the next erase, in one embodiment. This helps to improve endurance. In one embodiment, the erase depth is adjusted by determining a suitable erase verify level. Rather than (or in addition to) adjusting the erase verify level, the number of erase pulses that are performed after erase verify passes can be adjusted to adjust the erase depth.

    Abstract translation: 公开了通过动态擦除深度提高非易失性存储器的耐久性。 一组存储单元被擦除。 然后，擦除的存储单元中的至少一些被编程。 对存储单元进行编程通常会影响旨在保持擦除的那些存储单元的擦除阈值分布。 可以基于程序操作如何影响擦除阈值分布来调整下一个擦除的擦除深度。 作为一个示例，在编程之后测量擦除分布的上尾。 在一个实施例中，上尾部越高，下一次擦除越浅。 这有助于提高耐力。 在一个实施例中，通过确定合适的擦除验证电平来调整擦除深度。 除了（或除了）调整擦除验证电平之外，可以调整擦除验证通过之后执行的擦除脉冲数，以调整擦除深度。

    Selected word line dependent select gate voltage during program
    6.
    再颁专利
    Selected word line dependent select gate voltage during program 有权
    程序中所选字线相关选择栅极电压

    公开(公告)号：USRE45871E1

    公开(公告)日：2016-01-26

    申请号：US14284163

    申请日：2014-05-21

    Applicant: SanDisk Technologies Inc.

    Inventor： Chun-Hung Lai ,  Deepanshu Dutta ,  Shinji Sato ,  Gerrit Jan Hemink

    IPC: G11C11/34 ,  G11C11/56 ,  G11C16/10 ,  G11C16/04

    CPC classification number: G11C11/5628 ,  G11C16/0483 ,  G11C16/10

    Abstract: Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the location of the word line that is selected for programming, which may reduce or eliminate program disturb. The voltage applied to the gate of a select transistor of a NAND string may depend on the location of the selected word line. This could be either a source side or drain side select transistor. This may prevent or reduce program disturb that could result due to DIBL. This may also prevent or reduce program disturb that could result due to GIDL. A negative bias may be applied to the gate of a source side select transistor when programming at least some of the word lines. In one embodiment, progressively lower voltages are used for the gate of the drain side select transistor when programming progressively higher word lines.

    Abstract translation: 公开了用于操作非易失性存储器的方法和装置。 一个或多个编程条件取决于选择用于编程的字线的位置，这可以减少或消除程序干扰。 施加到NAND串的选择晶体管的栅极的电压可以取决于所选字线的位置。 这可以是源极侧或漏极侧选择晶体管。 这可能会阻止或减少由于DIBL而导致的程序干扰。 这也可以防止或减少由于GIDL可能导致的程序干扰。 当编程至少一些字线时，负偏压可以施加到源极侧选择晶体管的栅极。 在一个实施例中，当编程逐渐增加的字线时，逐渐降低的电压用于漏极侧选择晶体管的栅极。

    Dynamic erase depth for improved endurance of non-volatile memory
    7.
    发明授权
    Dynamic erase depth for improved endurance of non-volatile memory 有权
    动态擦除深度，以提高非易失性存储器的耐用性

    公开(公告)号：US09214240B2

    公开(公告)日：2015-12-15

    申请号：US14195265

    申请日：2014-03-03

    Applicant: SanDisk Technologies Inc.

    Inventor： Deepanshu Dutta ,  Chun-Hung Lai ,  Shih-Chung Lee ,  Ken Oowada ,  Masaaki Higashitani

    IPC: G11C16/04 ,  G11C16/14 ,  G11C16/34 ,  G11C16/16 ,  G11C11/56

    CPC classification number: G11C16/14 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/16 ,  G11C16/3427 ,  G11C16/3445 ,  G11C16/349

    Abstract: Improving endurance for non-volatile memory by dynamic erase depth is disclosed. A group of memory cells are erased. Then, at least some of the erased memory cells are programmed. Programming the memory cells typically impacts the erase threshold distribution of those memory cells that were intended to stay erased. The erase depth of the next erase can be adjusted based on how the program operation affects the erase threshold distribution. As one example, the upper tail of the erase distribution is measured after programming. The higher the upper tail, the shallower the next erase, in one embodiment. This helps to improve endurance. In one embodiment, the erase depth is adjusted by determining a suitable erase verify level. Rather than (or in addition to) adjusting the erase verify level, the number of erase pulses that are performed after erase verify passes can be adjusted to adjust the erase depth.

    Abstract translation: 公开了通过动态擦除深度提高非易失性存储器的耐久性。 一组存储单元被擦除。 然后，擦除的存储单元中的至少一些被编程。 对存储单元进行编程通常会影响旨在保持擦除的那些存储单元的擦除阈值分布。 可以基于程序操作如何影响擦除阈值分布来调整下一个擦除的擦除深度。 作为一个示例，在编程之后测量擦除分布的上尾。 在一个实施例中，上尾部越高，下一次擦除越浅。 这有助于提高耐力。 在一个实施例中，通过确定合适的擦除验证电平来调整擦除深度。 除了（或除了）调整擦除验证电平之外，可以调整擦除验证通过之后执行的擦除脉冲数，以调整擦除深度。

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