公开(公告)号：US08174908B2

公开(公告)日：2012-05-08

申请号：US12857439

申请日：2010-08-16

申请人： Se-Chun Park ,  Jong-Hyun Wang

发明人： Se-Chun Park ,  Jong-Hyun Wang

IPC分类号： G11C7/10

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C2211/5621 ,  G11C2211/5622 ,  G11C2216/14

摘要： A method of verifying data in a memory device having a page buffer for performing a program operation, a verifying operation and a read operation, includes: storing data to be programmed in a multi level cell of a first latching circuit in the page buffer; storing reference data set for the verifying operation in a second latching circuit; programming the data stored in the first latching circuit to the multi level cell; and verifying the programming of the data through a first node or a second node in the second latching circuit in accordance with a verifying voltage.

摘要翻译： 一种验证具有用于执行程序操作，验证操作和读取操作的页面缓冲器的存储器件中的数据的方法，包括：将待编程的数据存储在页缓冲器中的第一锁存电路的多电平单元中; 将用于验证操作的参考数据存储在第二锁存电路中; 将存储在第一锁存电路中的数据编程到多电平单元; 以及根据验证电压，通过第二锁存电路中的第一节点或第二节点验证数据的编程。

公开(公告)号：US08000154B2

公开(公告)日：2011-08-16

申请号：US12130931

申请日：2008-05-30

申请人： Chae Kyu Jang ,  Jong Hyun Wang ,  Suk Yun ,  Seong Hun Park

发明人： Chae Kyu Jang ,  Jong Hyun Wang ,  Suk Yun ,  Seong Hun Park

IPC分类号： G11C5/14

CPC分类号： G11C16/10 ,  G11C16/349

摘要： A non-volatile memory device comprises a voltage supplier comprising memory cells in which the voltage supplier supplies a positive set voltage to a bulk of a memory cell array at the time of a read operation of the memory cells and a controller for controlling the voltage supplier to set and supply a bulk voltage depending on a number of erase/program cycles of the memory cell array.

摘要翻译： 非易失性存储器件包括电压供应器，其包括存储器单元，其中电压供应器在存储器单元的读取操作时向存储单元阵列的大部分提供正设定电压，以及用于控制电压供应器 以根据存储器单元阵列的擦除/编程周期的数量来设置和提供体电压。

公开(公告)号：US07969786B2

公开(公告)日：2011-06-28

申请号：US12361231

申请日：2009-01-28

申请人： Jong Hyun Wang

发明人： Jong Hyun Wang

IPC分类号： G11C16/04

CPC分类号： G11C16/10

摘要： A method of programming nonvolatile memory devices. A program operation is performed by applying a dummy program pulse having a pulse width wider than a pulse width of a program start pulse. A program operation is performed by applying the program start pulse. It is then verified whether a program has been completed as a result of the program operation. A program operation is performed by applying a step-shaped dummy program pulse, which has a second pulse width and has been increased by a second step voltage. A program operation is performed by applying a program pulse having a first step voltage and a first pulse width. It is then verified whether a program has been completed as a result of the program operation.

摘要翻译： 一种编程非易失性存储器件的方法。 通过应用具有比程序开始脉冲的脉冲宽度更宽的脉冲宽度的虚拟编程脉冲来执行编程操作。 通过应用程序启动脉冲来执行编程操作。 然后，由程序运行结果验证程序是否已经完成。 通过应用具有第二脉冲宽度并已经增加第二阶梯电压的阶梯形伪程序脉冲来执行编程操作。 通过施加具有第一阶跃电压和第一脉冲宽度的编程脉冲来执行编程操作。 然后，由程序运行结果验证程序是否已经完成。

公开(公告)号：US20100284224A1

公开(公告)日：2010-11-11

申请号：US12839261

申请日：2010-07-19

申请人： Jong Hyun WANG

发明人： Jong Hyun WANG

IPC分类号： G11C16/04

CPC分类号： G11C16/12 ,  G11C16/0483

摘要： A flash memory device includes a plurality of memory blocks and a plurality of block selection circuits corresponding to the plurality of memory blocks. All of the block selection circuits are sequentially operated in response to block control signals, or two or more of the block selection circuits are operated in response to the block control signals.

摘要翻译： 闪速存储器件包括多个存储器块和对应于多个存储器块的多个块选择电路。 响应于块控制信号，顺序地操作所有块选择电路，或者响应于块控制信号操作两个或多个块选择电路。

公开(公告)号：US07706190B2

公开(公告)日：2010-04-27

申请号：US12163921

申请日：2008-06-27

申请人： Chang Won Yang ,  Jong Hyun Wang ,  Se Chun Park

发明人： Chang Won Yang ,  Jong Hyun Wang ,  Se Chun Park

IPC分类号： G11C16/34

CPC分类号： G11C16/3454 ,  G11C11/5628 ,  G11C16/3459 ,  G11C2211/5621

摘要： In a method of operating a non-volatile memory device subdivided verifications are performed by increasing verify voltages. Accordingly, threshold voltage distributions of memory cells can be narrowed and, therefore, the program performance of a flash memory device can be improved.

摘要翻译： 在操作非易失性存储器装置的方法中，通过增加验证电压来执行细分验证。 因此，存储器单元的阈值电压分布可以变窄，因此可以提高闪速存储器件的程序性能。

公开(公告)号：US07633813B2

公开(公告)日：2009-12-15

申请号：US11951936

申请日：2007-12-06

申请人： Jong-Hyun Wang ,  Se-Chun Park ,  Seong-Hun Park

发明人： Jong-Hyun Wang ,  Se-Chun Park ,  Seong-Hun Park

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C11/5635 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3413

摘要： An erase method of a memory cell array which includes at least one block having MLC is disclosed. The erase method includes shifting every threshold voltage distribution into a threshold voltage distribution having a highest level by pre-programming every cell in a block selected for erase, performing an erase operation on the pre-programmed memory block, performing a soft program and a verifying operation on the memory block, dividing the memory block into a first group and a second group when the memory block is passed, performing a verifying operation on the first group and performing a soft program and a verifying operation on the first group when the first group is not passed, and performing a verifying operation on the second group when the first group is passed and performing a soft program and a verifying operation on the second group when the second group is not passed.

摘要翻译： 公开了一种包括具有MLC的至少一个块的存储单元阵列的擦除方法。 擦除方法包括通过预先编程被选择用于擦除的块中的每个单元，对预编程的存储块执行擦除操作，执行软程序和验证来将每个阈值电压分布转换成具有最高电平的阈值电压分布 对所述存储块进行操作，当所述存储块通过时将所述存储块划分为第一组和第二组，对所述第一组执行验证操作，并且对所述第一组执行软程序和验证操作，当所述第一组 并且当第一组通过时对第二组执行验证操作，并且当第二组未通过时对第二组执行软程序和验证操作。

公开(公告)号：US20090172482A1

公开(公告)日：2009-07-02

申请号：US12130994

申请日：2008-05-30

申请人： Jong Hyun WANG ,  Chae Kyu Jang ,  Se Chun Park

发明人： Jong Hyun WANG ,  Chae Kyu Jang ,  Se Chun Park

IPC分类号： G11C29/08 ,  G06F11/26

CPC分类号： G11C29/44 ,  G11C29/82 ,  G11C2029/1208 ,  G11C2029/4402

摘要： Methods for performing a fail test, block management, erase operations and program operations are used in a nonvolatile memory device having a block switch devoid of a fuse and a PMOS transistor. A method for performing a fail test in a nonvolatile memory device includes performing a fail test for a memory cell block; storing good block information in a block information store associated with the corresponding block when the memory cell block is a good block; and repeating the performing and storing steps for all memory cell blocks.

摘要翻译： 在具有不具有熔丝和PMOS晶体管的块开关的非易失性存储器件中使用用于执行故障测试，块管理，擦除操作和编程操作的方法。 用于在非易失性存储器件中执行故障测试的方法包括执行存储器单元块的故障测试; 当所述存储器单元块是良好块时，将良好块信息存储在与相应块相关联的块信息存储器中; 并重复执行和存储所有存储单元块的步骤。

公开(公告)号：US07450432B2

公开(公告)日：2008-11-11

申请号：US11771792

申请日：2007-06-29

申请人： Jong Hyun Wang

发明人： Jong Hyun Wang

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621

摘要： A method of programming a most significant bit (MSB) data to a multi-level cell in a flash memory device including first and second cells includes performing a first program operation on the first cell using a first program voltage, the first cell being in a first state when the first program operation is performed on the first cell; if the first cell is determined to be in a second state after the first program operation, defining a second program voltage based on a result of comparing the first program voltage with a start voltage predefined for a second program operation; and performing the second program operation on the second cell using the second program voltage that has been defined according to a result of the comparison between the first program voltage and the start voltage.

摘要翻译： 一种将最高有效位（MSB）数据编程到包括第一和第二单元的闪存器件中的多电平单元的方法包括使用第一编程电压对第一单元执行第一编程操作，第一单元位于 当在第一单元上执行第一编程操作时的第一状态; 如果在第一编程操作之后确定第一单元处于第二状态，则基于将第一编程电压与为第二编程操作预定的启动电压进行比较的结果来定义第二编程电压; 以及使用根据第一编程电压和起始电压之间的比较结果定义的第二编程电压对第二单元执行第二编程操作。

公开(公告)号：US20080205138A1

公开(公告)日：2008-08-28

申请号：US11966007

申请日：2007-12-28

申请人： Jong Hyun Wang ,  Duck Ju Kim ,  Seong Hun Park ,  Chang Won Yang

发明人： Jong Hyun Wang ,  Duck Ju Kim ,  Seong Hun Park ,  Chang Won Yang

IPC分类号： G11C16/06 ,  G11C7/10

CPC分类号： G11C11/5628 ,  G11C16/0483 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： A memory device has memory cells that are Multi-Level Cells (MLCs). A memory cell array includes a plurality of cell strings, each string provided between a bit line and a common source line, wherein a positive voltage is applied to the common source line at the time of program verification. A page buffer is configured to program the MLCs, read memory cells, and perform program verification. This program verification is performed by sequentially increasing a voltage level of a bit line select signal until the bit line select signal reaches to a voltage that is sufficient to verify a programmed state of a selected cell in the memory cell array.

摘要翻译： 存储器件具有多层单元（MLC）的存储单元。 存储单元阵列包括多个单元串，每个串提供在位线和公共源极线之间，其中在编程验证时将正电压施加到公共源极线。 页面缓冲器被配置为对MLC进行编程，读取存储器单元并执行程序验证。 通过顺序地增加位线选择信号的电压电平直到位线选择信号达到足以验证存储单元阵列中选定单元的编程状态的电压来执行该程序验证。

公开(公告)号：US07072221B2

公开(公告)日：2006-07-04

申请号：US11014581

申请日：2004-12-16

申请人： Jong Hyun Wang

发明人： Jong Hyun Wang

IPC分类号： G11C16/06

CPC分类号： G11C16/10 ,  G11C16/32 ,  G11C16/3436

摘要： A flash memory device which can reduce the whole program or erase time and improve reliability by cycling, by storing a pulse width or a bias level for passing at least one bit of cells of a first page in a program or erase operation using an ISPP scheme, and using the stored pulse width or bias level as an initial pulse width or an initial bias level in a succeeding program operation or erase operation, and a method for driving the same.

摘要翻译： 一种闪速存储装置，其可以通过使用ISPP方案存储用于在程序或擦除操作中传送第一页的至少一位的单元的脉冲宽度或偏置电平来循环地减少整个程序或擦除时间并提高可靠性 并且在随后的编程操作或擦除操作中使用所存储的脉冲宽度或偏置电平作为初始脉冲宽度或初始偏置电平，以及用于驱动该脉冲宽度或偏置电平的方法。