公开(公告)号：US20240243018A1

公开(公告)日：2024-07-18

申请号：US18623690

申请日：2024-04-01

申请人： Applied Materials, Inc.

发明人： Wenjiao Wang ,  Joshua Maher ,  Xinhai Han ,  Deenesh Padhi ,  Tza-Jing Gung

IPC分类号： H01L21/66 ,  G03F7/00 ,  G06F30/398

CPC分类号： H01L22/12 ,  G06F30/398 ,  G03F7/705

摘要： Methods and systems are described for generating assessment maps. A method includes receiving a first data set reflecting distortions associated with a substrate and generating a second data set reflecting reduced noise in the distortions of the first data set. A third data set is generated by projecting a plurality of direction components associated with the second data set to a radial direction and a stress or strain map is generated indicating at least one of stress or strain exhibited by the substrate by determining a magnitude associated with a subset of the third data set.

公开(公告)号：US20230238289A1

公开(公告)日：2023-07-27

申请号：US18130500

申请日：2023-04-04

申请人： Applied Materials, Inc.

发明人： Wenjiao Wang ,  Joshua Maher ,  Xinhai Han ,  Deenesh Padhi ,  Tza-Jing Gung

IPC分类号： H01L21/66 ,  G06F30/398

CPC分类号： H01L22/12 ,  G06F30/398 ,  G03F7/705

摘要： Methods and systems are described for generating assessment maps. A method includes receiving a first vector map comprising a first set of vectors each indicating a distortion of a particular location on a substrate and generating a second vector map indicating a change in direction of a magnitude of the distortion of the particular location on the substrate. The method further includes generating a third vector map comprising vectors reflecting reduced noise in distortions across the plurality of locations on the substrate and generating a fourth vector map projecting a direction component of each vector component in the third set of vectors to a radial direction. The method further includes generating a fifth vector map by grouping the vectors of the fourth set of vectors and determining a magnitude associated with each group of vectors.

公开(公告)号：US20230113514A1

公开(公告)日：2023-04-13

申请号：US17541702

申请日：2021-12-03

申请人： Applied Materials, Inc.

发明人： Shih Chung Chen ,  Yongjing Lin ,  Chi-Chou Lin ,  Zhiyong Wang ,  Chih-Hsun Hsu ,  Mandyam Sriram ,  Tza-Jing Gung

IPC分类号： H01L21/768 ,  H01L21/311 ,  H01L21/02

摘要： Processing methods described herein comprise forming a metal gate film on a narrow feature and a wide feature and depositing a hard mask on the metal gate film. The hard mask forms on the metal gate film at a top, bottom and sidewalls of the wide feature and on a top of the narrow feature to cover the metal gate film. Some processing methods comprise oxidizing the metal gate film on the narrow feature to convert a portion of the metal gate film to a metal oxide film. Some processing methods comprise etching the metal oxide film from the narrow feature to leave a gradient etch profile. Some processing methods comprise filling the narrow feature and the wide feature with a gap fill material comprising one or more of a metal nitride, titanium nitride (TiN) or titanium oxynitride (TiON), the gap fill material substantially free of seams and voids.

公开(公告)号：US11562909B2

公开(公告)日：2023-01-24

申请号：US16881145

申请日：2020-05-22

申请人： Applied Materials, Inc.

发明人： Yu Lei ,  Xuesong Lu ,  Tae Hong Ha ,  Xianmin Tang ,  Andrew Nguyen ,  Tza-Jing Gung ,  Philip A. Kraus ,  Chung Nang Liu ,  Hui Sun ,  Yufei Hu

IPC分类号： H01L21/67 ,  H01L21/311 ,  H01L21/02 ,  H01J37/32 ,  H01L21/683 ,  H01L21/3105 ,  H01L21/8234

摘要： Described is a process to clean up junction interfaces for fabricating semiconductor devices involving forming low-resistance electrical connections between vertically separated regions. An etch can be performed to remove silicon oxide on silicon surface at the bottom of a recessed feature. Described are methods and apparatus for etching up the bottom oxide of a hole or trench while minimizing the effects to the underlying epitaxial layer and to the dielectric layers on the field and the corners of metal gate structures. The method for etching features involves a reaction chamber equipped with a combination of capacitively coupled plasma and inductive coupled plasma. CHxFy gases and plasma are used to form protection layer, which enables the selectively etching of bottom silicon dioxide by NH3—NF3 plasma. Ideally, silicon oxide on EPI is removed to ensure low-resistance electric contact while the epitaxial layer and field/corner dielectric layers are—etched only minimally or not at all.

公开(公告)号：US20220310364A1

公开(公告)日：2022-09-29

申请号：US17838860

申请日：2022-06-13

申请人： APPLIED MATERIALS, INC.

发明人： Halbert CHONG ,  Rong TAO ,  Jianxin LEI ,  Rongjun WANG ,  Keith A. Miller ,  Irena H. Wysok ,  Tza-Jing Gung ,  Xing Chen

IPC分类号： H01J37/32 ,  H01J37/34 ,  B08B5/00 ,  C23C14/50 ,  C23C14/34

摘要： Methods and apparatus for cleaning a process kit configured for processing a substrate are provided. For example, a process chamber for processing a substrate can include a chamber wall; a sputtering target disposed in an upper section of the inner volume; a pedestal including a substrate support having a support surface to support a substrate below the sputtering target; a power source configured to energize sputtering gas for forming a plasma in the inner volume; a process kit surrounding the sputtering target and the substrate support; and an ACT connected to the pedestal and a controller configured to tune the pedestal using the ACT to maintain a predetermined potential difference between the plasma in the inner volume and the process kit, wherein the predetermined potential difference is based on a percentage of total capacitance of the ACT and a stray capacitance associated with a grounding path of the process chamber.

公开(公告)号：US11289312B2

公开(公告)日：2022-03-29

申请号：US16438560

申请日：2019-06-12

申请人： APPLIED MATERIALS, INC.

发明人： Adolph M. Allen ,  Vanessa Faune ,  Zhong Qiang Hua ,  Kirankumar Neelasandra Savandaiah ,  Anantha K. Subramani ,  Philip A. Kraus ,  Tza-Jing Gung ,  Lei Zhou ,  Halbert Chong ,  Vaibhav Soni ,  Kishor Kalathiparambil

IPC分类号： H01J37/32 ,  H01J37/34 ,  C23C16/455 ,  C23C14/54

摘要： Embodiments of process kit shields and process chambers incorporating same are provided herein. In some embodiments a process kit configured for use in a process chamber for processing a substrate includes a shield having a cylindrical body having an upper portion and a lower portion; an adapter section configured to be supported on walls of the process chamber and having a resting surface to support the shield; and a heater coupled to the adapter section and configured to be electrically coupled to at least one power source of the processes chamber to heat the shield.

公开(公告)号：US10707116B2

公开(公告)日：2020-07-07

申请号：US15977380

申请日：2018-05-11

申请人： Applied Materials, Inc.

发明人： Jingmei Liang ,  Yong Sun ,  Jinrui Guo ,  Praket P. Jha ,  Jung Chan Lee ,  Tza-Jing Gung ,  Mukund Srinivasan

IPC分类号： H01L21/762 ,  H01L21/02 ,  H01L21/67 ,  C23C16/32 ,  C23C16/36 ,  C23C16/40 ,  H01J37/32 ,  C23C16/455 ,  C23C16/30 ,  C23C16/34 ,  C23C16/505 ,  C23C16/04

摘要： Implementations disclosed herein relate to methods for forming and filling trenches in a substrate with a flowable dielectric material. In one implementation, the method includes subjecting a substrate having at least one trench to a deposition process to form a flowable layer over a bottom surface and sidewall surfaces of the trench in a bottom-up fashion until the flowable layer reaches a predetermined deposition thickness, subjecting the flowable layer to a first curing process, the first curing process being a UV curing process, subjecting the UV cured flowable layer to a second curing process, the second curing process being a plasma or plasma-assisted process, and performing sequentially and repeatedly the deposition process, the first curing process, and the second curing process until the plasma cured flowable layer fills the trench and reaches a predetermined height over a top surface of the trench.

公开(公告)号：US09499901B2

公开(公告)日：2016-11-22

申请号：US13750318

申请日：2013-01-25

申请人： APPLIED MATERIALS, INC.

发明人： Yong Cao ,  Xianmin Tang ,  Adolph Miller Allen ,  Tza-Jing Gung

IPC分类号： C23C14/34 ,  C23C14/35 ,  C23C14/54 ,  H01J37/34

CPC分类号： C23C14/345 ,  C23C14/351 ,  C23C14/54 ,  H01J37/34

摘要： Methods for depositing a layer on a substrate are provided herein. In some embodiments, a method of depositing a metal-containing layer on a substrate in a physical vapor deposition (PVD) chamber may include applying RF power at a VHF frequency to a target comprising a metal disposed in the PVD chamber above the substrate to form a plasma from a plasma-forming gas; optionally applying DC power to the target; sputtering metal atoms from the target using the plasma while maintaining a first pressure in the PVD chamber sufficient to ionize a predominant portion of the sputtered metal atoms; and controlling the potential on the substrate to be the same polarity as the ionized metal atoms to deposit a metal-containing layer on the substrate.

摘要翻译： 本文提供了在基板上沉积层的方法。 在一些实施例中，在物理气相沉积（PVD）室中在衬底上沉积含金属层的方法可以包括以VHF频率将RF功率施加到包括设置在衬底上方的PVD室中的金属的靶，以形成 来自等离子体形成气体的等离子体; 可选地向目标施加DC电力; 使用等离子体从靶中溅射金属原子，同时保持PVD室中的第一压力足以离子化主要部分的溅射金属原子; 并且将基板上的电位控制为与电离金属原子相同的极性，以在基板上沉积含金属层。

公开(公告)号：US20160225590A1

公开(公告)日：2016-08-04

申请号：US14985688

申请日：2015-12-31

申请人： Applied Materials, Inc.

发明人： Joseph F. Aubuchon ,  Tza-Jing Gung ,  Travis Lee Koh ,  Nattaworn Nuntaworanuch ,  Sheng-Chin Kung ,  Steven Lane ,  Kartik Ramaswamy ,  Yang Yang

IPC分类号： H01J37/32

CPC分类号： H01J37/32669 ,  H01J37/3211

摘要： Embodiments described herein generally relate to plasma process apparatus. In one embodiment, the plasma process apparatus includes a plasma source assembly. The plasma source assembly may include a first coil, a second coil surrounding the first coil, and a magnetic device disposed outside the first and inside the second coil. The magnet enables additional tuning which improves uniformity control of the processes on the substrate.

摘要翻译： 本文描述的实施例一般涉及等离子体处理装置。 在一个实施例中，等离子体处理装置包括等离子体源组件。 等离子体源组件可以包括第一线圈，围绕第一线圈的第二线圈和设置在第二线圈的第一和内侧的磁性装置。 该磁体可实现额外的调谐，从而提高基板上工艺的均匀性控制。

公开(公告)号：US11637107B2

公开(公告)日：2023-04-25

申请号：US17351223

申请日：2021-06-17

申请人： Applied Materials, Inc.

发明人： Tom Ho Wing Yu ,  Nobuyuki Sasaki ,  Jianxin Lei ,  Wenting Hou ,  Rongjun Wang ,  Tza-Jing Gung

IPC分类号： H01L27/108

摘要： Bit line stacks and methods of forming bit line stacks are described herein. A bit line stack comprises: a polysilicon layer; an adhesion layer on the polysilicon layer; a barrier metal layer on the adhesion layer; an interface layer on the barrier metal layer; a resistance reducing layer on the interface layer; and a conductive layer on the resistance reducing layer. A bit line stack having the resistance reducing layer has a resistance at least 5% lower than a comparable bit line stack without the resistance reducing layer. The resistance reducing layer may include silicon oxide or silicon nitride. The resistance reducing layer may be formed using one or more of a physical vapor deposition (PVD), a radio frequency-PVD, a pulsed-PVD, chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering process.