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公开(公告)号:US11830824B2
公开(公告)日:2023-11-28
申请号:US17214411
申请日:2021-03-26
发明人: Amirhasan Nourbakhsh , Lan Yu , Joseph F. Salfelder , Ki Cheol Ahn , Tyler Sherwood , Siddarth Krishnan , Michael Jason Fronckowiak , Xing Chen
IPC分类号: H01L23/00 , H01L21/304 , H01L21/308 , H01L21/311
CPC分类号: H01L23/562 , H01L21/304 , H01L21/3086 , H01L21/31111
摘要: Exemplary methods of processing a semiconductor substrate may include forming a layer of dielectric material on the semiconductor substrate. The methods may include performing an edge exclusion removal of the layer of dielectric material. The methods may include forming a mask material on the semiconductor substrate. The mask material may contact the dielectric material at an edge region of the semiconductor substrate. The methods may include patterning an opening in the mask material overlying a first surface of the semiconductor substrate. The methods may include etching one or more trenches through the semiconductor substrate.
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公开(公告)号:US20220254886A1
公开(公告)日:2022-08-11
申请号:US17169916
申请日:2021-02-08
发明人: Ashish Pal , El Mehdi Bazizi , Siddarth Krishnan , Xing Chen , Lan Yu , Tyler Sherwood
IPC分类号: H01L29/36 , H01L29/872 , H01L21/02 , H01L21/265 , H01L21/285 , H01L21/3065 , H01L29/66
摘要: Exemplary methods of forming a semiconductor structure may include forming a doped silicon layer on a semiconductor substrate. A level of doping may be increased at an increasing distance from the semiconductor substrate. The methods may include etching the doped silicon layer to define a trench extending to the semiconductor substrate. The doped silicon layer may define a sloping sidewall of the trench. The trench may be characterized by a depth of greater than or about 30 μm. The methods may include lining the trench with a first oxide material. The methods may include depositing a second oxide material within the trench. The methods may include forming a contact to produce a power device.
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公开(公告)号:US20220310531A1
公开(公告)日:2022-09-29
申请号:US17214411
申请日:2021-03-26
发明人: Amirhasan Nourbakhsh , Lan Yu , Joseph F. Salfelder , Ki Cheol Ahn , Tyler Sherwood , Siddarth Krishnan , Michael Jason Fronckowiak , Xing Chen
IPC分类号: H01L23/00 , H01L21/311 , H01L21/308 , H01L21/304
摘要: Exemplary methods of processing a semiconductor substrate may include forming a layer of dielectric material on the semiconductor substrate. The methods may include performing an edge exclusion removal of the layer of dielectric material. The methods may include forming a mask material on the semiconductor substrate. The mask material may contact the dielectric material at an edge region of the semiconductor substrate. The methods may include patterning an opening in the mask material overlying a first surface of the semiconductor substrate. The methods may include etching one or more trenches through the semiconductor substrate.
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公开(公告)号:US20220310364A1
公开(公告)日:2022-09-29
申请号:US17838860
申请日:2022-06-13
发明人: Halbert CHONG , Rong TAO , Jianxin LEI , Rongjun WANG , Keith A. Miller , Irena H. Wysok , Tza-Jing Gung , Xing Chen
摘要: Methods and apparatus for cleaning a process kit configured for processing a substrate are provided. For example, a process chamber for processing a substrate can include a chamber wall; a sputtering target disposed in an upper section of the inner volume; a pedestal including a substrate support having a support surface to support a substrate below the sputtering target; a power source configured to energize sputtering gas for forming a plasma in the inner volume; a process kit surrounding the sputtering target and the substrate support; and an ACT connected to the pedestal and a controller configured to tune the pedestal using the ACT to maintain a predetermined potential difference between the plasma in the inner volume and the process kit, wherein the predetermined potential difference is based on a percentage of total capacitance of the ACT and a stray capacitance associated with a grounding path of the process chamber.
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公开(公告)号:US11705490B2
公开(公告)日:2023-07-18
申请号:US17169916
申请日:2021-02-08
发明人: Ashish Pal , El Mehdi Bazizi , Siddarth Krishnan , Xing Chen , Lan Yu , Tyler Sherwood
IPC分类号: H01L21/02 , H01L29/36 , H01L29/872 , H01L29/66 , H01L21/285 , H01L21/3065 , H01L21/265
CPC分类号: H01L29/36 , H01L21/02164 , H01L21/26513 , H01L21/28537 , H01L21/3065 , H01L29/66143 , H01L29/872
摘要: Exemplary methods of forming a semiconductor structure may include forming a doped silicon layer on a semiconductor substrate. A level of doping may be increased at an increasing distance from the semiconductor substrate. The methods may include etching the doped silicon layer to define a trench extending to the semiconductor substrate. The doped silicon layer may define a sloping sidewall of the trench. The trench may be characterized by a depth of greater than or about 30 μm. The methods may include lining the trench with a first oxide material. The methods may include depositing a second oxide material within the trench. The methods may include forming a contact to produce a power device.
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公开(公告)号:US11512387B2
公开(公告)日:2022-11-29
申请号:US16846505
申请日:2020-04-13
发明人: Chao Du , Xing Chen , Keith A. Miller , Jothilingam Ramalingam , Jianxin Lei
摘要: Methods and apparatus for passivating a target are provided herein. For example, a method includes a) supplying an oxidizing gas into an inner volume of the process chamber; b) igniting the oxidizing gas to form a plasma and oxidize at least one of a target or target material deposited on a process kit disposed in the inner volume of the process chamber; and c) performing a cycle purge comprising: c1) providing air into the process chamber to react with the at least one of the target or target material deposited on the process kit; c2) maintaining a predetermined pressure for a predetermined time within the process chamber to generate a toxic by-product caused by the air reacting with the at least one of the target or target material deposited on the process kit; and c3) exhausting the process chamber to remove the toxic by-product.
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公开(公告)号:US20220310363A1
公开(公告)日:2022-09-29
申请号:US17838855
申请日:2022-06-13
发明人: Halbert CHONG , Rong TAO , Jianxin LEI , Rongjun WANG , Keith A. Miller , Irena H. Wysok , Tza-Jing Gung , Xing Chen
摘要: Methods and apparatus for cleaning a process kit configured for processing a substrate are provided. For example, a process chamber for processing a substrate can include a chamber wall; a sputtering target disposed in an upper section of the inner volume; a pedestal including a substrate support having a support surface to support a substrate below the sputtering target; a power source configured to energize sputtering gas for forming a plasma in the inner volume; a process kit surrounding the sputtering target and the substrate support; and an ACT connected to the pedestal and a controller configured to tune the pedestal using the ACT to maintain a predetermined potential difference between the plasma in the inner volume and the process kit, wherein the predetermined potential difference is based on a percentage of total capacitance of the ACT and a stray capacitance associated with a grounding path of the process chamber.
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公开(公告)号:US20210319989A1
公开(公告)日:2021-10-14
申请号:US16846502
申请日:2020-04-13
发明人: Halbert CHONG , Rong TAO , Jianxin LEI , Rongjun WANG , Keith A. Miller , Irena H. Wysok , Tza-Jing Gung , Xing Chen
摘要: Methods and apparatus for cleaning a process kit configured for processing a substrate are provided. For example, a process chamber for processing a substrate can include a chamber wall; a sputtering target disposed in an upper section of the inner volume; a pedestal including a substrate support having a support surface to support a substrate below the sputtering target; a power source configured to energize sputtering gas for forming a plasma in the inner volume; a process kit surrounding the sputtering target and the substrate support; and an ACT connected to the pedestal and a controller configured to tune the pedestal using the ACT to maintain a predetermined potential difference between the plasma in the inner volume and the process kit, wherein the predetermined potential difference is based on a percentage of total capacitance of the ACT and a stray capacitance associated with a grounding path of the process chamber.
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公开(公告)号:US11661651B2
公开(公告)日:2023-05-30
申请号:US17838805
申请日:2022-06-13
发明人: Chao Du , Xing Chen , Keith A. Miller , Jothilingam Ramalingam , Jianxin Lei
CPC分类号: C23C14/3414 , C23C14/022 , C23C14/5846 , C23C14/5873 , H01J37/32449 , H01J37/32844 , H01J37/32981
摘要: Methods and apparatus for passivating a target are provided herein. For example, a method includes a) supplying an oxidizing gas into an inner volume of the process chamber; b) igniting the oxidizing gas to form a plasma and oxidize at least one of a target or target material deposited on a process kit disposed in the inner volume of the process chamber; and c) performing a cycle purge comprising: c1) providing air into the process chamber to react with the at least one of the target or target material deposited on the process kit; c2) maintaining a predetermined pressure for a predetermined time within the process chamber to generate a toxic by-product caused by the air reacting with the at least one of the target or target material deposited on the process kit; and c3) exhausting the process chamber to remove the toxic by-product.
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