公开(公告)号：US20240313079A1

公开(公告)日：2024-09-19

申请号：US18185242

申请日：2023-03-16

Applicant: Applied Materials, Inc.

Inventor： Sefa Dag ,  El Mehdi Bazizi ,  Gaurav Thareja ,  Avgerinos V. Gelatos ,  Gang Shen

IPC: H01L29/45 ,  H01L21/285

CPC classification number: H01L29/45 ,  H01L21/28518

Abstract: The present technology includes semiconductor devices and methods with improved contact resistivity. Semiconductor devices include a substrate base, a silicon oxide disposed on the base defining one or more features, a bi-metallic silicide layer disposed on the substrate in the one or more features, and at least a first metal layer. The bi-metallic silicide layer includes a first metal, a second metal different than the first metal, and a silicon containing compound, and includes greater than or about 0.8 E+14 per cm−2 second metal atoms. The first metal layer includes the first metal and overlies the bi-metallic silicide layer.

公开(公告)号：US12074196B2

公开(公告)日：2024-08-27

申请号：US17370835

申请日：2021-07-08

Applicant: Applied Materials, Inc.

Inventor： Ashish Pal ,  Yi Zheng ,  El Mehdi Bazizi

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0634 ,  H01L29/66712 ,  H01L29/7802

Abstract: Embodiments of processing a substrate are provided herein. In some embodiments, a method of processing a substrate includes: depositing, via a first epitaxial growth process, an n-doped silicon material onto a substrate to form an n-doped layer while adjusting a ratio of dopant precursor to silicon precursor so that a dopant concentration of the n-doped layer increases from a bottom of the n-doped layer to a top of the n-doped layer; etching the n-doped layer to form a plurality of trenches having sidewalls that are tapered and a plurality of n-doped pillars therebetween; and filling the plurality of trenches with a p-doped material via a second epitaxial growth process to form a plurality of p-doped pillars.

公开(公告)号：US11899376B1

公开(公告)日：2024-02-13

申请号：US17900124

申请日：2022-08-31

Applicant: Applied Materials, Inc.

Inventor： Prayudi Lianto ,  Liu Jiang ,  Marvin Louis Bernt ,  El Mehdi Bazizi ,  Guan Huei See

IPC: G03F9/00 ,  G03F7/00

CPC classification number: G03F7/70633 ,  G03F9/7088

Abstract: A method for forming alignment marks leverages pad density and critical dimensions (CDs). In some embodiments, the method includes forming first and second alignment marks on a first substrate and a second substrate where the alignment marks have a width within 5% of the associated CD of copper pads on the respective substrates and forming a first and second dummy patterns around the first and second alignment marks. The first and second dummy patterns have dummy pattern densities within 5% of the respective copper pad density of the first and second substrates and CDs within 5% of the respective copper pad CDs. In some embodiments, alignment marks with physical dielectric material protrusions and recesses on opposite substrate surfaces may further enhance bonding.

公开(公告)号：US20240332388A1

公开(公告)日：2024-10-03

申请号：US18609650

申请日：2024-03-19

Applicant: Applied Materials, Inc.

Inventor： Byeong Chan Lee ,  Benjamin Colombeau ,  Nicolas Breil ,  Ashish Pal ,  El Mehdi Bazizi ,  Veeraraghavan S. Basker ,  Balasubramanian Pranatharthiharan ,  Pratik B. Vyas ,  Gregory Costrini

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L21/823807 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/0847 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: One or more embodiments of the disclosure are directed to methods of forming semiconductor devices, e.g., gate-all-around (GAA) transistors that are used in FEOL and/or BEOL processes. The processes described herein may be integrated and performed in any suitable cluster tool. Some embodiments of the disclosure are directed to cavity shaping processes. Further embodiments of the disclosure are directed to logic transistors with wrap-around backside source/drain contact.

公开(公告)号：US20240290884A1

公开(公告)日：2024-08-29

申请号：US18441824

申请日：2024-02-14

Applicant: Applied Materials, Inc.

Inventor： El Mehdi Bazizi ,  Sai Hooi Yeong ,  Benjamin Colombeau ,  Balasubramanian Pranatharthiharan ,  Hui Zhao ,  Ashish Pal

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/7846 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: The present technology includes semiconductor devices with improved stress in a channel region. The semiconductor devices include a substrate, a source region, a drain region, a channel region that includes at least one channel located between the source and the drain, a first gate region, and a second gate region. The first gate region includes a self-aligned single diffusion break, and the second gate region includes a first gate enclosing the channel between the source region and the drain region. The self-aligned single diffusion break also contains a stressed dielectric material having a stress of about 500 MPa or greater.

公开(公告)号：US20240258375A1

公开(公告)日：2024-08-01

申请号：US18160949

申请日：2023-01-27

Applicant: Applied Materials, Inc.

Inventor： Ashish Pal ,  Pratik B. Vyas ,  El Mehdi Bazizi ,  Stephen Weeks ,  Ludovico Megalini ,  Siddarth Krishnan

IPC: H01L29/10 ,  H01L21/04 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L29/105 ,  H01L21/046 ,  H01L29/1608 ,  H01L29/66068

Abstract: A silicon carbide transistor may be formed with a channel that includes a p-doped region between n-doped source and drain regions. A counter-doped region may be formed at the top of the channel directly underneath the gate oxide. Instead of using the conventional doping levels for the p-doped region, the doping concentration may be increase to be greater than about 1e18 cm3. The transistor may also include pocket regions on one or both sides of the channel. The pocket regions may be formed in the counter-doped region and may extend up to the gate oxide. These improvements individually and/or in combination may increase the current in the channel of the transistor without significantly increasing the threshold voltage beyond acceptable operating limits.

公开(公告)号：US20240234531A1

公开(公告)日：2024-07-11

申请号：US18538273

申请日：2023-12-13

Applicant: Applied Materials, Inc.

Inventor： Sai Hooi Yeong ,  Liu Jiang ,  Susmit Singha Roy ,  Abhijit Basu Mallick ,  Benjamin Colombeau ,  El Mehdi Bazizi ,  Balasubramanian Pranatharthiharan

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L21/823807 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/775 ,  H01L29/78696

Abstract: Semiconductor devices (e.g., gate-all-around (GAA) devices), process tools for manufacturing GAA devices and methods of manufacturing GAA devices, and inner spacer liners and inner spacers for GAA devices, are described. The methods comprise performing a chemical vapor deposition (CVD) process to form an amorphous silicon liner and an inner spacer within a superlattice structure formed on a top surface of a semiconductor substrate. The superlattice structure has a plurality of semiconductor material layers (e.g., silicon germanium (SiGe)) and a corresponding plurality of channel layers (e.g., silicon (Si)). The amorphous silicon liner is conformally formed along the GAA device, including along the recessed semiconductor material layers and the corresponding plurality of channel layers, and the inner spacer is formed directly on the amorphous silicon liner. One or more operations of the methods described herein are performed in situ in an integrated processing tool system.

公开(公告)号：US20220246742A1

公开(公告)日：2022-08-04

申请号：US17583355

申请日：2022-01-25

Applicant: Applied Materials, Inc.

Inventor： Ashish Pal ,  El Mehdi Bazizi ,  Benjamin Colombeau ,  Myungsun Kim

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L29/15

Abstract: Horizontal gate-all-around devices and methods of manufacturing are described. The hGAA devices comprise a fully-depleted silicon-on-insulator (FD-SOI) under the channel layers in the same footprint as the hGAA. The buried dielectric insulating layer of the FD-SOI comprises one or more of silicon oxide (SiOx), silicon nitride (SiN), silicon carbide (SiC), and a high-k material, and the buried dielectric insulating layer has a thickness in a range of from 0 nm to 10 nm.

公开(公告)号：US20220059698A1

公开(公告)日：2022-02-24

申请号：US17000546

申请日：2020-08-24

Applicant: Applied Materials, Inc.

Inventor： Ashish Pal ,  Mehdi Saremi ,  El Mehdi Bazizi ,  Benjamin Colombeau

IPC: H01L29/78

Abstract: Examples of the present technology include processing methods to incorporate stress in a channel region of a semiconductor transistor. The methods may include depositing a stressed material on an adjacent layer, where the adjacent layer is disposed between the stressed material and semiconductor material having an incorporated dopant. The adjacent layer may be characterized by an increased stress level after the deposition of the stressed material. The method may further include heating the stressed material and the adjacent layer, and removing the stressed material from the adjacent layer. The adjacent layer retains at least a portion of the increased stress after the removal of the stressed material. Examples of the present technology also include semiconductor structures having a conductive layer with first stress, and an intermediate layer with second stress in contact with the conductive layer. The second tensile stress may be at least ten times the first tensile stress.

公开(公告)号：US11145726B2

公开(公告)日：2021-10-12

申请号：US16654904

申请日：2019-10-16

Applicant: Applied Materials, Inc.

Inventor： Sushant Mittal ,  Ashish Pal ,  El Mehdi Bazizi ,  Angada Sachid

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: Semiconductor structures may include a substrate. The structures may include a gate structure overlying the substrate and formed in a first direction across the substrate. The structures may include a fin overlying the substrate and formed in a second direction across the substrate. The second direction may be orthogonal to the first direction, and the fin may intersect the gate structure. The structures may include a source/drain material formed about the fin. The structures may include a through-contact material extending vertically above the source/drain material. The structures may include a metal material extending vertically above the through-contact material. An interface between the metal material and the through-contact material may be characterized by a non-planar profile.