公开(公告)号：US12074196B2

公开(公告)日：2024-08-27

申请号：US17370835

申请日：2021-07-08

Applicant: Applied Materials, Inc.

Inventor： Ashish Pal ,  Yi Zheng ,  El Mehdi Bazizi

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0634 ,  H01L29/66712 ,  H01L29/7802

Abstract: Embodiments of processing a substrate are provided herein. In some embodiments, a method of processing a substrate includes: depositing, via a first epitaxial growth process, an n-doped silicon material onto a substrate to form an n-doped layer while adjusting a ratio of dopant precursor to silicon precursor so that a dopant concentration of the n-doped layer increases from a bottom of the n-doped layer to a top of the n-doped layer; etching the n-doped layer to form a plurality of trenches having sidewalls that are tapered and a plurality of n-doped pillars therebetween; and filling the plurality of trenches with a p-doped material via a second epitaxial growth process to form a plurality of p-doped pillars.

公开(公告)号：US20240290885A1

公开(公告)日：2024-08-29

申请号：US18441886

申请日：2024-02-14

Applicant: Applied Materials, Inc.

Inventor： Sai Hooi Yeong ,  Benjamin Colombeau ,  Balasubramanian Pranatharthiharan ,  El Mehdi Bazizi ,  Hui Zhao ,  Ashish Pal

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/768 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/7846 ,  H01L21/76224 ,  H01L21/76831 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: The present technology includes semiconductor devices with improved stress in a channel region. The semiconductor device includes a substrate, a source region, a drain region, a channel region that includes at least one channel located between the source and the drain. Devices include a first gate region having a first self-aligned single diffusion break in a n-MOS region, and a second gate region includes having a self-aligned single diffusion break in a p-MOS region. The second self-aligned single diffusion break also contains a liner and a compressive stressed material, where the stressed metal fill exhibits a compressive stress of about 350 MPa or greater.

公开(公告)号：US20240014214A1

公开(公告)日：2024-01-11

申请号：US18219993

申请日：2023-07-10

Applicant: Applied Materials, Inc.

Inventor： Sai Hooi Yeong ,  Jody A. Fronheiser ,  Benjamin Colombeau ,  Balasubramanian Pranatharthiharan ,  El Mehdi Bazizi ,  Ashish Pal

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  H01L29/15 ,  H01L21/8238 ,  H01L29/06

CPC classification number: H01L27/0924 ,  H01L29/66545 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/775 ,  H01L29/15 ,  H01L29/66439 ,  H01L21/823807 ,  H01L29/0673

Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a semiconductor material between source regions and drain regions of the device. The method includes formation of a cladding material on a first material followed by a dry oxidation process resulting rearrangement of the cladding material and first material.

公开(公告)号：US20230170400A1

公开(公告)日：2023-06-01

申请号：US17994520

申请日：2022-11-28

Applicant: Applied Materials, Inc.

Inventor： Ashish Pal ,  Benjamin Colombeau ,  El Mehdi Bazizi ,  Balasubramanian Pranatharthiharan

IPC: H01L29/66 ,  H01L23/528 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/417 ,  H01L29/775 ,  H01L21/02 ,  H01L29/40

CPC classification number: H01L29/66439 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/775 ,  H01L21/02603 ,  H01L21/02532 ,  H01L29/401 ,  H01L29/66545

Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes front side processing to form a source/drain cavity and filling the cavity with a sacrificial layer. The sacrificial layer is then removed during processing of the backside to form a backside power rail via that is filled with a metal fill.

公开(公告)号：US20230068312A1

公开(公告)日：2023-03-02

申请号：US17897378

申请日：2022-08-29

Applicant: Applied Materials, Inc.

Inventor： Suketu Arun Parikh ,  Ashish Pal ,  El Mehdi Bazizi ,  Andrew Yeoh ,  Nitin K. Ingle ,  Arvind Sundarrajan ,  Guan Huei See ,  Martinus Maria Berkens ,  Sameer A. Deshpande ,  Balasubramanian Pranatharthiharan ,  Yen-Chu Yang

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/48

Abstract: Semiconductor devices and methods of manufacturing the same are described. Transistors are fabricated using a standard process flow. A via opening extending from the top surface of the substrate to a bottom surface of the wafer device is formed, thus allowing nano TSV for high density packaging, as well as connecting the device to the backside power rail. A metal is deposited in the via opening, and the bottom surface of the wafer device is bound to a bonding wafer. The substrate is optionally thinned, and a contact electrically connected to the metal is formed.

公开(公告)号：US20230067331A1

公开(公告)日：2023-03-02

申请号：US17896223

申请日：2022-08-26

Applicant: Applied Materials, Inc.

Inventor： Ashish Pal ,  El Mehdi Bazizi ,  Benjamin Colombeau

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/16 ,  H01L29/15

Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes forming a bottom dielectric isolation (BDI) layer on a substrate and depositing a template material in the source/drain trench. The template material is etched and then crystallized. Epitaxially growth of the source and drain regions then proceeds, with growth advantageously occurring on the bottom and sidewalls of the source and drain regions.

公开(公告)号：US20220254886A1

公开(公告)日：2022-08-11

申请号：US17169916

申请日：2021-02-08

Applicant: Applied Materials, Inc.

Inventor： Ashish Pal ,  El Mehdi Bazizi ,  Siddarth Krishnan ,  Xing Chen ,  Lan Yu ,  Tyler Sherwood

IPC: H01L29/36 ,  H01L29/872 ,  H01L21/02 ,  H01L21/265 ,  H01L21/285 ,  H01L21/3065 ,  H01L29/66

Abstract: Exemplary methods of forming a semiconductor structure may include forming a doped silicon layer on a semiconductor substrate. A level of doping may be increased at an increasing distance from the semiconductor substrate. The methods may include etching the doped silicon layer to define a trench extending to the semiconductor substrate. The doped silicon layer may define a sloping sidewall of the trench. The trench may be characterized by a depth of greater than or about 30 μm. The methods may include lining the trench with a first oxide material. The methods may include depositing a second oxide material within the trench. The methods may include forming a contact to produce a power device.

公开(公告)号：US20230299199A1

公开(公告)日：2023-09-21

申请号：US18324711

申请日：2023-05-26

Applicant: Applied Materials, Inc.

Inventor： Ashish Pal ,  Mehdi Saremi ,  El Mehdi Bazizi ,  Benjamin Colombeau

IPC: H01L29/78

CPC classification number: H01L29/7842

Abstract: Examples of the present technology include processing methods to incorporate stress in a channel region of a semiconductor transistor. The methods may include depositing a stressed material on an adjacent layer, where the adjacent layer is disposed between the stressed material and semiconductor material having an incorporated dopant. The adjacent layer may be characterized by an increased stress level after the deposition of the stressed material. The method may further include heating the stressed material and the adjacent layer, and removing the stressed material from the adjacent layer. The adjacent layer retains at least a portion of the increased stress after the removal of the stressed material. Examples of the present technology also include semiconductor structures having a conductive layer with first stress, and an intermediate layer with second stress in contact with the conductive layer. The second tensile stress may be at least ten times the first tensile stress.

公开(公告)号：US11735467B2

公开(公告)日：2023-08-22

申请号：US17558848

申请日：2021-12-22

Applicant: Applied Materials, Inc.

Inventor： Ashish Pal ,  Gaurav Thareja ,  Sankuei Lin ,  Ching-Mei Hsu ,  Nitin K. Ingle ,  Ajay Bhatnagar ,  Anchuan Wang

IPC: H01L21/764 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L29/417

CPC classification number: H01L21/764 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/41791

Abstract: Processing methods may be performed to form an airgap spacer on a semiconductor substrate. The methods may include forming a spacer structure including a first material and a second material different from the first material. The methods may include forming a source/drain structure. The source/drain structure may be offset from the second material of the spacer structure by at least one other material. The methods may also include etching the second material from the spacer structure to form the airgap. The source/drain structure may be unexposed to etchant materials during the etching.

公开(公告)号：US20230260909A1

公开(公告)日：2023-08-17

申请号：US18106643

申请日：2023-02-07

Applicant: Applied Materials, Inc.

Inventor： Andrew Yeoh ,  Benjamin Colombeau ,  Balasubramanian Pranatharthiharan ,  El Mehdi Bazizi ,  Ashish Pal

IPC: H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/775 ,  H01L21/02 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L23/5286 ,  H01L21/02532 ,  H01L21/02603 ,  H01L29/401 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439

Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes forming a diffusion break opening on the backside and filling with a diffusion break material to serve as a planarization stop. In some embodiments, a single diffusion break opening is formed. In other embodiments, a mixed diffusion break opening is formed.