公开(公告)号：US20230061392A1

公开(公告)日：2023-03-02

申请号：US17897372

申请日：2022-08-29

Applicant: Applied Materials, Inc.

Inventor： Suketu Arun Parikh ,  Ashish Pal ,  El Mehdi Bazizi ,  Andrew Yeoh ,  Nitin K. Ingle ,  Arvind Sundarrajan ,  Guan Huei See ,  Martinus Maria Berkens ,  Sameer A. Deshpande ,  Balasubramanian Pranatharthiharan ,  Yen-Chu Yang

IPC: H01L21/768 ,  H01L21/304 ,  H01L21/306 ,  H01L21/762

Abstract: Semiconductor devices and methods of manufacturing the same are described. A silicon wafer is provided and a buried etch stop layer is formed on the silicon wafer. The wafer is then subjected to device and front-end processing. After front-end processing, the wafer undergoes hybrid bonding, and then the wafer is thinned. To thin the wafer, the silicon substrate layer, which has a starting first thickness, is ground to a second thickness, the second thickness less than the first thickness. After grinding, the silicon wafer is subjected to chemical mechanical planarization (CMP), followed by etching and CMP buffing, to reduce the thickness of the silicon to a third thickness, the third thickness less than the second thickness.

公开(公告)号：US20240281584A1

公开(公告)日：2024-08-22

申请号：US18170335

申请日：2023-02-16

Applicant: Applied Materials, Inc.

Inventor： Martinus Maria Berkens ,  Bhuvaneshwari Ayyagari ,  Simon Johannes Klaver ,  Vinod Reddy ,  Rene Gerardus Maria Beugels ,  Andres Llopis Lozano

IPC: G06F30/337 ,  G06F30/392

CPC classification number: G06F30/337 ,  G06F30/392

Abstract: A method of automatically generating standard cells may include receiving a definition of a circuit for a standard cell. The definition may include one or more semiconductor devices. The method may also include identifying a plurality of slices that implement a device in the one or more semiconductor devices. Each of the plurality of slices may include a partial layout for the device. The method may further include combining more than one of the plurality of slices into a combined layout to implement the device when forming the standard cell.

公开(公告)号：US20230068312A1

公开(公告)日：2023-03-02

申请号：US17897378

申请日：2022-08-29

Applicant: Applied Materials, Inc.

Inventor： Suketu Arun Parikh ,  Ashish Pal ,  El Mehdi Bazizi ,  Andrew Yeoh ,  Nitin K. Ingle ,  Arvind Sundarrajan ,  Guan Huei See ,  Martinus Maria Berkens ,  Sameer A. Deshpande ,  Balasubramanian Pranatharthiharan ,  Yen-Chu Yang

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/48

Abstract: Semiconductor devices and methods of manufacturing the same are described. Transistors are fabricated using a standard process flow. A via opening extending from the top surface of the substrate to a bottom surface of the wafer device is formed, thus allowing nano TSV for high density packaging, as well as connecting the device to the backside power rail. A metal is deposited in the via opening, and the bottom surface of the wafer device is bound to a bonding wafer. The substrate is optionally thinned, and a contact electrically connected to the metal is formed.

公开(公告)号：US20230064183A1

公开(公告)日：2023-03-02

申请号：US17897375

申请日：2022-08-29

Applicant: Applied Materials, Inc.

Inventor： Suketu Arun Parikh ,  Ashish Pal ,  El Mehdi Bazizi ,  Andrew Yeoh ,  Nitin K. Ingle ,  Arvind Sundarrajan ,  Guan Huei See ,  Martinus Maria Berkens ,  Sameer A. Deshpande ,  Balasubramanian Pranatharthiharan ,  Yen-Chu Yang

IPC: H01L23/528 ,  H01L21/768 ,  H01L29/786 ,  H01L29/423

Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes front side processing to form a deep source/drain cavity and filling the cavity with a sacrificial material. The sacrificial material is then removed during processing of the backside to form a backside power rail via that is filled with a metal fill.